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cy7c63310 cy7c638xx encore? ii low-speed usb peripheral controlle r cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document 38-08035 rev. *i revised september 26, 2006 1.0 features ?encore tm ii usb??enhanced component reduction? ? crystalless oscillator with support for an external clock. the internal oscillator eliminates the need for an external crystal or resonator ? two internal 3.3v regulators and internal usb pull-up resistor ? configurable io for real-world interface without external components ? usb specification compliance ? conforms to usb specification, version 2.0 ? conforms to usb hid specification, version 1.1 ? supports one low-speed usb device address ? supports one control endpoint and two data endpoints ? integrated usb transceiver with dedicated 3.3v regulator for usb signalling and d- pull up. ? enhanced 8-bit microcontroller ? harvard architecture ? m8c cpu speed can be up to 24 mhz or sourced by an external clock signal ? internal memory ? up to 256 bytes of ram ? up to eight kbytes of flash including eerom emulation ? interface can autoconfigure to operate as ps/2 or usb ? no external components for switching between ps/2 and usb modes ? no gpio pins needed to manage dual-mode capability ? low power consumption ? typically 10 ma at 6 mhz ?10 a sleep ? in-system re-programmability ? allows easy firmware update ? general purpose i/o ports ? up to 20 general purpose i/o (gpio) pins ? high current drive on gpio pins. configurable 8- or 50- ma/pin current sink on designated pins ? each gpio port supports high-impedance inputs, configurable pull up, open drain output, cmos/ttl inputs, and cmos output ? maskable interrupts on all i/o pins ? a dedicated 3.3v regulator for the usb phy. aids in signalling and d-line pull-up ? 125 ma 3.3v voltage regulator can power external 3.3v devices ? 3.3v i/o pins ? 4 i/o pins with 3.3v logic levels ? each 3.3v pin supports high-impedance input, internal pull up, open drain output or traditional cmos output ? spi serial communication ? master or slave operation ? configurable up to 4 mbit/second transfers in the master mode ? supports half duplex single data line mode for optical sensors ? 2-channel 8-bit or 1-channel 16- bit capture timer registers. capture timer registers stor e both rising and falling edge times ? two registers each for two input pins ? separate registers for risi ng and falling edge capture ? simplifies interface to rf inputs for wireless applications ? internal low-power wake-up timer during suspend mode ? periodic wake-up with no external components ? 12-bit programmable interval timer with interrupts ? advanced development tools based on cypress microsystems psoc? tools ? watchdog timer (wdt) ? low-voltage detection with user-configurable threshold voltages ? operating voltage from 4.0v to 5.5vdc ? operating temperature from 0?70c ? available in 16/18-pin pdip, 16/18/24-pin soic, 24-pin qsop and 32-lead qfn packages ? industry standard programmer support 1.1 applications the cy7c63310/cy7c638xx is targeted for the following applications: ? pc hid devices ? mice (optomechanical, optical, trackball) ?gaming ? joysticks ? game pad ? general-purpose ? barcode scanners ? pos terminal ? consumer electronics ?toys ? remote controls ? security dongles
cy7c63310 cy7c638xx document 38-08035 rev. *i page 2 of 74 2.0 introduction cypress has reinvented its leadership position in the low- speed usb market with a new family of innovative microcon- trollers. introducing encore ii usb ? ?enhanced component reduction.? cypress has leveraged its design expertise in usb solutions to advance its family of low-speed usb micro- controllers, which enable peripheral developers to design new products with a minimum number of components. the encore ii usb technology builds on to the encore family. the encore family has an integr ated oscillator that eliminates the external crystal or resonator, reducing overall cost. also integrated into this chip are other external components commonly found in low-speed usb applications such as pull- up resistors, wake-up circuitry, and a 3.3v regulator. all of this reduces the overall system cost. the encore ii is an 8-bit flash-programmable microcontroller with integrated low-speed usb in terface. the instruction set has been optimized specifically for usb and ps/2 operations, although the microcontrollers can be used for a variety of other embedded applications. the encore ii features up to 20 general-purpose i/o (gpio) pins to support usb, ps/2 and other applications. the i/o pins are grouped into four ports (port 0 to 3). the pins on port 0 and port 1 may each be configured individually while the pins on ports 2 and 3 may only be configured as a group. each gpio port supports high-impedance inputs, configurable pull up, open drain output, cmos/ttl inputs, and cmos output with up to five pins that support programmable drive strength of up to 50 ma sink current. gpio port 1 features four pins that interface at a voltage level of 3.3 volts. additionally, each i/o pin can be used to generate a gpio interrupt to the microcon- troller. each gpio port has its own gpio interrupt vector; in addition gpio port 0 has three dedicated pins that have independent interrupt vectors (p0.2 - p0.4). the encore ii features an internal oscillator. with the presence of usb traffic, the internal oscillator can be set to precisely tune to usb timing requirements (24 mhz 1.5%). optionally, an external 12 mhz or 24 mhz clock can be used to provide a higher precision re ference for usb operation. the clock generator provides the 12 mhz and 24 mhz clocks that remain internal to the microcontroller. the encore ii also has a 12-bit programmable interval timer and a 16-bit free- running timer with capture timer registers. in addition, the encore ii includes a watchdog timer and a vectored interrupt controller the encore ii has up to eight kbytes of flash for user?s code and up to 256 bytes of ram for stack space and user variables. the power-on reset circuit detects logic when power is applied to the device, resets the logic to a known state, and begins executing instructions at flash address 0x0000. when power falls below a programmable trip voltage generates reset or may be configured to generate interrupt. there is a low- voltage detect circuit that detects when v cc drops below a programmable trip voltage. it may be configurable to generate an lvd interrupt to inform the processor about the low-voltage event. por and lvd share the same interrupt. there is no separate interrupt for each. the watchdog timer can be used to ensure the firmware never gets stalled in an infinite loop. the microcontroller supports 22 maskable interrupts in the vectored interrupt controller. interrupt sources include a usb bus reset, lvr/por, a programmable interval timer, a 1.024-ms output from the fr ee running timer, three usb endpoints, two capture timers, four gpio ports, three port 0 pins, two spi, a 16-bit free running timer wrap, an internal sleep timer, and a bus active interrupt. the sleep timer causes periodic interrupts when enabled. the usb endpoints interrupt after a usb transaction complete is on the bus. the capture timers interrupt whenever a new timer value is saved due to a selected gpio edge event. a total of seven gpio interrupts support both ttl or cmos thresholds. for additional flexi- bility, on the edge sensitive gpio pins, the interrupt polarity is programmable to be either rising or falling. the free-running 16-bit timer provides two interrupt sources: the 1.024 ms outputs and the free running counter wrap interrupt. the programmable interval timer can provide up to 1 sec resolution and provides an interrupt everytime it expires. these timers can be used to measure the duration of an event under firmware control by reading the desired timer at the start and at the end of an event, then calculating the difference between the two values. the two 8-bit capture timer registers save a programmable 8-bit range of the free-running timer when a gpio edge occurs on the two capture pins (p0.5, p0.6). the two 8-bit captures can be ganged into a single 16-bit capture. the encore ii includes an integrated usb serial interface engine (sie) that allows the ch ip to easily interface to a usb host. the hardware supports one usb device address with three endpoints. the usb d+ and d? pins can optionally be used as ps/2 sclk and sdata signals so that products can be designed to respond to either usb or ps/ 2 modes of operation. ps/2 operation is supported with internal 5 k ? pull-up resistors on p1.0 (d+) and p1.1 (d?) and an interrupt to signal the start of ps/2 activity. in usb mode, the integrated 1.5 k ? pull-up resistor on d? can be controlled under firmware. no external components are necessary for dual usb and ps/2 systems, and no gpio pins need to be dedicated to switching between modes. the encore ii supports in-system programming by using the d+ and d? pins as the serial programming mode interface. the programming protocol is not usb. 3.0 conventions in this document, bit positions in the registers are shaded to indicate which members of the encore ii family implement the bits. available in all encore ii family members cy7c638xx only
cy7c63310 cy7c638xx document 38-08035 rev. *i page 3 of 74 4.0 logic block diagram figure 4-1. cy7c63310/cy7c638xx block diagram internal 24 mhz oscillator 3.3v regulator clock control por / low-voltage detect watchdog timer ram up to 256 byte m8c cpu flash up to 8k byte up to 14 extended i/o pins low-speed usb/ps2 transceiver and pull-up up to 6 gpio pins wakeup timer 16-bit free running timer 12-bit timer 4 3vio/spi pins vdd interrupt control low-speed usb sie external clock
cy7c63310 cy7c638xx document 38-08035 rev. *i page 4 of 74 5.0 packages/pinouts figure 5-1. package configurations 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 nc p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.0 p2.0 p1.5/smosi p1.3/ssel p3.1 p3.0 v cc p1.2/vreg p1.1/d? p1.0/d+ 14 p1.4/sclk 10 p2.1 nc v ss 12 13 7 8 int0/p0.2 p0.1 24 23 p1.7 p1.6/smiso 24-pin qsop cy7c63823 1 2 3 4 6 7 8 10 11 12 13 15 16 18 17 ssel/p1.3 sclk/p1.4 smosi/p1.5 smiso/p1.6 p0.7 tio0/p0.5 p1.2/vreg p1.1/d? p1.0/d+ p0.0 p0.1 p0.2/int0 18-pin pdip v cc 9 tio1/p0.6 int2/p0.4 p0.3/int1 cy7c63813 5 14 p1.7 v ss 1 2 3 4 6 7 8 9 10 11 13 14 16 15 ssel/p1.3 sclk/p1.4 smosi/p1.5 smiso/p1.6 tio0/p0.5 int1/p0.3 p1.2 p1.1/d? p1.0/d+ p0.1 p0.2/int0 p0.0 16-pin pdip v cc int2/p0.4 5 12 tio1/p0.6 v ss top view cy7c63310 cy7c63801 16-pin pdip 1 2 3 4 6 7 8 9 10 11 13 14 16 15 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.1 v ss p1.6/smiso p1.4/sclk p1.3/ssel p1.1/d? p1.0/d+ v cc 16-pin soic p1.5/smosi p0.0 5 12 int0/p0.2 p1.2 cy7c63310 cy7c63801 16-pin soic 1 2 3 4 6 7 8 10 11 12 13 15 16 18 17 p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int0/p0.2 p0.0 p1.7 p1.5/smosi p1.4/sclk p1.2/vreg v cc p1.1/d? 18-pin soic p1.6/smiso 9 p0.1 v ss p1.0/d+ cy7c63813 5 14 int1/p0.3 p1.3/ssel 1 2 3 4 5 6 9 11 15 16 17 18 19 20 22 21 nc p0.7 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.0 p2.0 p1.6/smiso p3.0 p1.4/sclk p3.1 p1.2/vreg p1.3/ssel v cc p1.1/d? 14 p1.5/smosi 10 p2.1 v ss p1.0/d+ 12 13 7 8 int0/p0.2 p0.1 24 23 nc p1.7 24-pin soic cy7c63823 1 2 3 4 6 7 8 9 10 11 13 14 16 15 tio1/p0.6 tio0/p0.5 int2/p0.4 int1/p0.3 p0.1 v ss p1.6/smiso p1.4/sclk p1.3/ssel p1.1/d? p1.0/d+ v cc p1.5/smosi p0.0 5 12 int0/p0.2 p1.2/vreg CY7C63803 16-pin soic 1 2 3 4 5 6 21 19 23 25 22 26 20 24 18 9 8 12 13 10 14 16 11 17 15 7 27 28 32 30 29 31 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1 p0.0 p2.1 p2.0 nc nc nc vss p1.0/d+ p1.1/d- vdd nc nc p1.3/ssel p3.0 p3.1 p1.4/sclk p1.5/smosi p1.6/miso p1.7 p0.7 nc nc nc nc nc p1.2/vreg 32-lead qfn cy7c63833
cy7c63310 cy7c638xx document 38-08035 rev. *i page 5 of 74 5.1 pinouts assignments table 5-1. pin assignments 32 qfn 24 qsop 24 soic 18 sioc 18 pdip 16 soic 16 pdip name description 21 19 18 p3.0 gpio port 3 ? configured as a group (byte) 22 20 19 p3.1 9 11 11 p2.0 gpio port 2 ? configured as a group (byte) 81010 p2.1 14 14 13 10 15 9 13 p1.0/d+ gpio port 1 bit 0/usb d+ [1] if this pin is used as a general purpose output, it will draw current. this pin must be configured as an input to reduce current draw. 15 15 14 11 16 10 14 p1.1/d? gpio port 1 bit 1/usb d? [1] if this pin is used as a general purpose output, it will draw current. this pin must be configured as an input to reduce current draw. 18 17 16 13 18 12 16 p1.2/vreg gpio port 1 bit 2?configured individually. 3.3v if regulator is enabled. (the 3.3v regulator is not available in the cy7c63310 and cy7c63801.) a 1- f min, 2- f max capacitor is required on vreg output. 20 18 17 14 1 13 1 p1.3/ssel gpio port 1 bit 3?configured individually. alternate function is ssel signal of the spi bus ttl voltage thresholds. although vreg is not available with the cy7c63310, 3.3v i/o is still available. 23 21 20 15 2 14 2 p1.4/sclk gpio port 1 bit 4?configured individually. alternate function is sclk signal of the spi bus ttl voltage thresholds. although vreg is not available with the cy7c63310, 3.3v i/o is still available. 24 22 21 16 3 15 3 p1.5/smosi gpio port 1 bit 5?configured individually. alternate function is smosi signal of the spi bus ttl voltage thresholds. although vreg is not available with the cy7c63310, 3.3v i/o is still available. 25 23 22 17 4 16 4 p1.6/smiso gpio port 1 bit 6?configured individually. alternate function is smiso signal of the spi bus ttl voltage thresholds. although vreg is not available with the cy7c63310, 3.3v i/o is still available. 26 24 23 18 5 p1.7 gpio port 1 bit 7?configured individually. ttl voltage threshold. 7 9 9 8 13 7 11 p0.0 gpio port 0 bit 0?configured individually. on cy7c638xx and cy7c63310, external clock input when configured as clock in. 6 8 8 7 12 6 10 p0.1 gpio port 0 bit 1?configured individually on cy7c638xx and cy7c63310, clock output when configured as clock out. 5 7 7 6 11 5 9 p0.2/int0 gpio port 0 bit 2?configured individually optional rising edge interrupt int0 4 6 6 5 10 4 8 p0.3/int1 gpio port 0 bit 3?configured individually optional rising edge interrupt int1 3 5 5 4 9 3 7 p0.4/int2 gpio port 0 bit 4?configured individually optional rising edge interrupt int2 note 1. p1.0(d+) and p1.1(d-) pins must be in i/o mode when used as gpio and in i sb mode.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 6 of 74 6.0 cpu architecture this family of microcontrollers is based on a high performance, 8-bit, harvard-architecture mi croprocessor. five registers control the primary operation of the cpu core. these registers are affected by various instruct ions, but are not directly acces- sible through the register space by the user. the 16-bit program counter register (cpu_pc) allows for direct addressing of the full eight kbytes of program memory space. the accumulator register (cpu_a) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. the index register (cpu_x) holds an offset value that is used in the indexed addressing modes. typically, this is used to address a block of data within the data memory space. the stack pointer register (cpu_sp) holds the address of the current top-of-stack in the data memory space. it is affected by the push, pop, lcall, call, reti, and ret instructions, which manage the software stack. it can also be affected by the swap and add instructions. the flag register (cpu_f) has three status bits: zero flag bit [1]; carry flag bit [2]; supervisory state bit [3]. the global interrupt enable bit [0] is used to globally enable or disable interrupts. the user cannot m anipulate the supervisory state status bit [3]. the flags are af fected by arithmetic, logic, and shift operations. the manner in which each flag is changed is dependent upon the instruction being executed (i.e., and, or, xor). see table 8-1 . 2 4 4 3 8 2 6 p0.5/tio0 gpio port 0 bit 5?configured individually alternate function timer capture inputs or timer output tio0 1 3 3 2 7 1 5 p0.6/tio1 gpio port 0 bit 6?configured individually alternate function timer capture inputs or timer output tio1 32 2 2 1 6 p0.7 gpio port 0 bit 7?configured individually not present in the 16 pin pdip or soic package 10 1 1 nc no connect 11 12 24 nc no connect 12 nc no connect 17 nc no connect 19 nc no connect 27 nc no connect 28 nc no connect 29 nc no connect 30 nc no connect 31 nc no connect 16 16 15 12 17 11 15 vcc supply 13 13 12 9 14 8 12 v ss ground table 5-1. pin assignments (continued) 32 qfn 24 qsop 24 soic 18 sioc 18 pdip 16 soic 16 pdip name description table 6-1. cpu regist ers and register names register register name flags cpu_f program counter cpu_pc accumulator cpu_a stack pointer cpu_sp index cpu_x
cy7c63310 cy7c638xx document 38-08035 rev. *i page 7 of 74 7.0 cpu registers 7.1 flags register the flags register can only be set or reset with logical instruction. table 7-1. cpu flags register (cpu_f) [r/w] bit # 7 6 5 4 3 2 1 0 field reserved xio super carry zero global ie read/write ? ? ? r/w r rwrwrw default 00000010 bit [7:5]: reserved bit 4: xio set by the user to select between the register banks 0 = bank 0 1 = bank 1 bit 3: super indicates whether the cpu is executing us er code or supervisor code. (this code cannot be accessed directly by the user) 0 = user code 1 = supervisor code bit 2: carry set by cpu to indicate whether there has been a ca rry in the previous logi cal/arithmetic operation 0 = no carry 1 = carry bit 1: zero set by cpu to indicate whether there has been a zero result in the previous logical/arithmetic operation 0 = not equal to zero 1 = equal to zero bit 0: global ie determines whether all interrupts are enabled or disabled 0 = disabled 1 = enabled note: cpu_f register is only readable with explicit register address 0xf7. the or f, expr and and f, expr instructions must be used to set and clear the cpu_f bits table 7-2. cpu accumulator register (cpu_a) bit # 7 6 5 4 3 2 1 0 field cpu accumulator [7:0] read/write ???????? default 00000000 bit [7:0]: cpu accumulator [7:0] 8-bit data value holds the result of any logical/arithm etic instruction that uses a source addressing mode table 7-3. cpu x register (cpu_x) bit # 7 6 5 4 3 2 1 0 field x [7:0] read/write ???????? default 00000000 bit [7:0]: x [7:0] 8-bit data value holds an index for any instru ction that uses an indexed addressing mode table 7-4. cpu stack pointer register (cpu_sp) bit # 7 6 5 4 3 2 1 0 field stack pointer [7:0] read/write ???????? default 00000000 bit [7:0]: stack pointer [7:0] 8-bit data value holds a pointer to the current top-of-stack
cy7c63310 cy7c638xx document 38-08035 rev. *i page 8 of 74 7.2 addressing modes 7.2.1 source immediate the result of an instruction using this addressing mode is placed in the a register, the f re gister, the sp register, or the x register, which is specified as part of the instruction opcode. operand 1 is an immediate value that serves as a source for the instruction. arithm etic instructions requ ire two sources; the second one is the a or the x re gister specified in the opcode. instructions using this addressing mode are two bytes in length. examples 7.2.2 source direct the result of an instruction using this addressing mode is placed in either the a register or the x register, which is specified as part of the inst ruction opcode. operand 1 is an address that points to a location in either the ram memory space or the register space that is the source for the instruction. arithmet ic instructions require two sources; the second source is the a register or x regist er specified in the opcode. instructions using th is addressing mode are two bytes in length. examples 7.2.3 source indexed the result of an instruction using this addressing mode is placed in either the a register or the x register, which is specified as part of the instruction opcode. operand 1 is added to the x register forming an address that points to a location in either the ram memory space or the register space that is the source for the instruction. arit hmetic instructions require two sources; the second source is the a register or x register specified in the opcode. instructions using this addressing mode are two bytes in length. examples table 7-5. cpu program counter high register (cpu_pch) bit # 7 6 5 4 3 2 1 0 field program counter [15:8] read/write ???????? default 00000000 bit [7:0]: program counter [15:8] 8-bit data value holds the higher byte of the program counter table 7-6. cpu program counter low register (cpu_pcl) bit # 7 6 5 4 3 2 1 0 field program counter [7:0] read/write ???????? default 00000000 bit [7:0]: program counter [7:0] 8-bit data value holds the lower byte of the program counter table 7-7. source immediate opcode operand 1 instruction immediate value add a, 7 ;in this case, the immediate value; of 7 is added with the accumulator,; and the result is placed in the; accumulator. mov x, 8 ;in this case, the imm ediate value; of 8 is moved to the x register. and f, 9 ;in this case, the immediate value; of 9 is logi- cally anded with the f; register and the result is placed; in the f register. table 7-8. source direct opcode operand 1 instruction source address add a, [7] ;in this case, the; value in; the ram memory location at; address 7 is added with the; accumulator, and the result; is placed in the accumulator. mov x, reg[8] ;in this case, the value in; the register space at address; 8 is moved to the x register. table 7-9. source indexed opcode operand 1 instruction source index add a, [x+7] ;in this case, the value in; the mem- ory location at; address x + 7 is added with; the accumulator, and the; result is placed in the; accumula- tor. mov x, reg[x+8] ;in this case, the value in; the register space at; address x + 8 is moved to; the x register.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 9 of 74 7.2.4 destination direct the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is an address that points to the location of the result. the source for the instruction is either the a register or the x register, which is specif ied as part of the instruction opcode. arithmetic instructions require two sources; the second source is the location specified by operand 1. instruc- tions using this addressing mode are two bytes in length. examples 7.2.5 destination indexed the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x register forming the address that points to the location of the result. the source for the instruction is the a register. arithmetic instructions require two sources; the second source is the location specified by operand 1 added with the x register. instructions using this addressing mode are two bytes in length. example 7.2.6 destination direct source immediate the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is the address of the result. the source for the instruction is operand 2, which is an immediate value. arithmetic instructions require two sources; the second source is the location specified by oper and 1. instructions using this addressing mode are three bytes in length. examples 7.2.7 destination indexed source immediate the result of an instruction using this addressing mode is placed within either the ram memory space or the register space. operand 1 is added to the x register to form the address of the result. the source for the instruction is operand 2, which is an immediate value. arithmetic instructions require two sources; the second source is the location specified by operand 1 added with the x regi ster. instructions using this addressing mode are three bytes in length. examples 7.2.8 destination direct source direct the result of an instruction using this addressing mode is placed within the ram memory. operand 1 is the address of the result. operand 2 is an addr ess that points to a location in the ram memory that is the source for the instruction. this addressing mode is only valid on the mov instruction. the instruction using this addressing mode is three bytes in length. table 7-10. destination direct opcode operand 1 instruction destination address add [7], a ;in this case, the value in; the memory location at; address 7 is added with the; accumulator, and the result; is placed in the memory; location at address 7. the; accumulator is unchanged. mov reg[8], a ;in this case, the accumulator is moved to the register space location at address 8. the accumulator is unchanged. table 7-11. destination indexed opcode operand 1 instruction destination index add [x+7], a ;in this case, the value in the; memory location at address x+7; is added with the accumulator,; and the result is placed in; the memory location at address; x+7. the accumulator is; unchanged. table 7-12. destination direct source immediate opcode operand 1 operand 2 instruction destination address immediate value add [7], 5 ;in this case, value in the memory location at address 7 is added to the immediate value of 5, and the result is placed in the memory location at address 7. mov reg[8], 6 ;in this case, the immediate; value of 6 is moved into the; register space location at; address 8. table 7-13. destination indexed source immediate opcode operand 1 operand 2 instruction destination index immediate value add [x+7], 5 ;in this case, the value in; the mem- ory location at; address x+7 is added with; the immediate value of 5,; and the result is placed; in the memory location at; address x+7. mov reg[x+8], 6 ;in this case, the immediate value of 6 is moved; into the location in the; register space at; address x+8. table 7-14. destination direct source direct opcode operand 1 operand 2 instruction destination address source address
cy7c63310 cy7c638xx document 38-08035 rev. *i page 10 of 74 example 7.2.9 source indirect post increment the result of an instruction using this addressing mode is placed in the accumulator. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source of the instruction. the indirect address is incremented as part of the instruction execution. this addressing mode is only valid on the mvi instruction. the instruction us ing this addressing mode is two bytes in length. refer to the psoc designer: assembly language user guide for further details on mvi instruction. example 7.2.10 destination indi rect post increment the result of an instruction using this addressing mode is placed within the memory space. operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the destination of the instruction. the indirect addre ss is incremented as part of the instruction execution. the sour ce for the instruction is the accumulator. this addressing mode is only valid on the mvi instruction. the instruction usin g this addressing mode is two bytes in length. example mov [7], [8] ;in this case, the value in the; memory loca- tion at address 8 is; moved to the memory location at; address 7. table 7-15. source indirect post increment opcode operand 1 instruction source address address mvi a, [8] ;in this case, the value in the; memory loca- tion at address 8 is an indirect address. the memory location pointed to by the indirect address is moved into the accumulator. the indirect address is then incremented. table 7-16. destination indirect post increment opcode operand 1 instruction destination address address mvi [8], a ;in this case, the value in; the memory location at; address 8 is an indirect; address. the accumulator is; moved into the memory location pointed to by the indirect address. the indirect; address is then incremented.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 11 of 74 8.0 instruction set summary the instruction set is summarized in table 8-1 numerically and serves as a quick reference. if more information is needed, the instruction set summary tables are described in detail in the psoc designer assembly language user guide (available on the www.cypress. com web site). table 8-1. instruction set summary sorted numerically by opcode order [2, 3] opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags opcode hex cycles bytes instruction format flags 00 15 1 ssc 2d 8 2 or [x+expr], a z 5a 5 2 mov [expr], x 01 4 2 add a, expr c, z 2e 9 3 or [expr], expr z 5b 4 1 mov a, x z 02 6 2 add a, [expr] c, z 2f 10 3 or [x+expr], expr z 5c 4 1 mov x, a 03 7 2 add a, [x+expr] c, z 30 9 1 halt 5d 6 2 mov a, reg[expr] z 04 7 2 add [expr], a c, z 31 4 2 xor a, expr z 5e 7 2 mov a, reg[x+expr] z 05 8 2 add [x+expr], a c, z 32 6 2 xor a, [expr] z 5f 10 3 mov [expr], [expr] 06 9 3 add [expr], expr c, z 33 7 2 xor a, [x+expr] z 60 5 2 mov reg[expr], a 07 10 3 add [x+expr], expr c, z 34 7 2 xor [expr], a z 61 6 2 mov reg[x+expr], a 08 4 1 push a 35 8 2 xor [x+expr], a z 62 8 3 mov reg[expr], expr 09 4 2 adc a, expr c, z 36 9 3 xor [expr], expr z 63 9 3 mov reg[x+expr], expr 0a 6 2 adc a, [expr] c, z 37 10 3 xor [x+expr], expr z 64 4 1 asl a c, z 0b 7 2 adc a, [x+expr] c, z 38 5 2 add sp, expr 65 7 2 asl [expr] c, z 0c 7 2 adc [expr], a c, z 39 5 2 cmp a, expr if (a=b) z=1 if (a cy7c63310 cy7c638xx document 38-08035 rev. *i page 12 of 74 9.0 memory organization 9.1 flash program memory organization figure 9-1. program memory space with interrupt vector table after reset address 16-bit pc 0x0000 program execution begins here after a reset 0x0004 por/lvd 0x0008 int0 0x000c spi transmitter empty 0x0010 spi receiver full 0x0014 gpio port 0 0x0018 gpio port 1 0x001c int1 0x0020 ep0 0x0024 ep1 0x0028 ep2 0x002c usb reset 0x0030 usb active 0x0034 1 ms interval timer 0x0038 programmable interval timer 0x003c timer capture 0 0x0040 timer capture 1 0x0044 16-bit free running timer wrap 0x0048 int2 0x004c ps2 data low 0x0050 gpio port 2 0x0054 gpio port 3 0x0058 reserved 0x005c reserved 0x0060 reserved 0x0064 sleep timer 0x0068 program memory begins here (if below interrupts not used, program memory can start lower) 0x0bff 3 kb ends here (cy7c63310) 0x0fff 4 kb ends here (cy7c63801) 0x1fff 8 kb ends here (cy7c638x3)
cy7c63310 cy7c638xx document 38-08035 rev. *i page 13 of 74 9.2 data memory organization the cy7c63310/638xx microcontrollers provide up to 256 bytes of data ram. 9.3 flash this section describes the flash block of the encore ii. much of the user-visible flash func tionality including programming and security are implemented in the m8c supervisory read only memory (srom). encore ii flash has an endurance of 1000 cycles and a 10 year data retention capability. 9.3.1 flash programming and security all flash programming is performed by code in the srom. the registers that control the flas h programming are only visible to the m8c cpu when it is executing out of srom. this makes it impossible to read, write or erase the flash by bypassing the security mechanisms implemented in the srom. customer firmware can only program the flash via srom calls. the data or code images can be sourced via any interface with the appropriate support firmware. this type of programming requires a ?boot-loader??a piece of firmware resident on the flash. for safety reasons this boot-loader must not be overwritten duri ng firmware rewrites. the flash provides four extra auxiliary rows that are used to hold flash block protection flags, boot time calibration values, configuration tables, and any de vice values. the routines for accessing these auxiliary rows are documented in the srom section. the auxiliary rows ar e not affected by the device erase function. 9.3.2 in-system programming most designs that include an encore ii part will have a usb connector attached to the usb d+/d? pins on the device. these designs require the ability to program or reprogram a part through these two pins alone. encore ii devices enable this type of in-system programming by using the d+ and d? pins as the serial programming mode interface. this allows an exte rnal controller to cause the encore ii part to enter serial programming mode and then to use the test queue to issue flash access functions in the srom. the programming protocol is not usb. 9.4 srom the srom holds code that is us ed to boot the part, calibrate circuitry, and perform flash operations. ( table 9-1 lists the srom functions.) the functions of the srom may be accessed in normal user code or operating from flash. the srom exists in a separate memory space from user code. the srom functions are accessed by executing the super- visory system call instruction (ssc), which has an opcode of 00h. prior to executing the ssc the m8c?s accumulator needs to be loaded with the desired srom function code from table 9-1 . undefined functions will cause a halt if called from user code. the srom functions are executing code with calls; therefore, the functions requ ire stack space. with the exception of reset, all of the srom functions have a parameter block in sram that must be configured before executing the ssc. ta ble 9-2 lists all possible parameter block variables. the meaning of each parameter, with regards to a specific srom function, is described later in this chapter. figure 9-2. data memory organization after reset address 8-bit psp 0x00 stack begins here and grows upward. top of ram memory 0xff table 9-1. srom function codes function code function name stack space 00h swbootreset 0 01h readblock 7 02h writeblock 10 03h eraseblock 9 05h eraseall 11 06h tableread 3 07h checksum 3
cy7c63310 cy7c638xx document 38-08035 rev. *i page 14 of 74 two important variables that ar e used for all functions are key1 and key2. these variables are used to help discrim- inate between valid sscs and inadvertent sscs. key1 must always have a value of 3ah, while key2 must have the same value as the stack pointer when the srom function begins execution. this would be the stack pointer value when the ssc opcode is executed, plus th ree. if either of the keys do not match the expected values , the m8c will halt (with the exception of the swbootreset function). the following code puts the correct value in key1 and key2. the code starts with a halt, to force the program to jump directly into the setup code and not run into it. halt sscop: mov [key1], 3ah mov x, sp mov a, x add a, 3 mov [key2], a 9.4.1 return codes the srom also features return codes and lockouts. return codes aid in the determination of success or failure of a particular function. the return code is stored in key1?s position in the parameter block. the checksum and tableread functions do not have return codes because key1?s position in the paramete r block is used to return other data. read, write, and erase operations may fail if the target block is read or write protected. block protection levels are set during device programming. the eraseall function overwrites da ta in addition to leaving the entire user flash in the eras e state. the eraseall function loops through the number of flash macros in the product, executing the following sequence: erase, bulk program all zeros, erase. after all the user space in all the flash macros are erased, a second loop erases and then programs each protection block with zeros. 9.5 srom function descriptions 9.5.1 swbootreset function the srom function, swbootreset, is the function that is responsible for transitioning the device from a reset state to running user code. the swboot reset function is executed whenever the srom is entered with an m8c accumulator value of 00h: the sram parameter block is not used as an input to the function. this will happen, by design, after a hardware reset, bec ause the m8c's accu mulator is reset to 00h or when user code executes the ssc instruction with an accumulator value of 00h. the swbootreset function will not execute when the ssc instruction is executed with a bad key value and a non-zero function code. an encore ii device will execute the halt instruction if a bad value is given for either key1 or key2. the swbootreset function verifies the integrity of the calibration data by way of a 16-bit checksum, before releasing the m8c to run user code. 9.5.2 readblock function the readblock function is used to read 64 contiguous bytes from flash: a block. the first thing this function does is to check the protection bits and determine if the desired blockid is readable. if read protection is turned on, the readblock function will exit setting the accumulator and key2 back to 00h. key1 will have a value of 01h, indicating a read failure. if read protection is not enabled, the function will read 64 bytes from the flash using a romx instruction and store the results in sram using an mvi instruction. the first of the 64 bytes will be stored in sram at the address indicated by the value of the pointer parameter. when the readblo ck completes successfully the accumulator, key1 and key2 will all have a value of 00h. 9.5.3 writeblock function the writeblock function is used to store data in the flash. data is moved 64 bytes at a time from sram to flash using this function. the first thing the writeblock function does is to check the protection bits and determine if the desired blockid is writable. if write pr otection is turned on, the write- block function will exit setting the accumulator and key2 back to 00h. key1 will have a value of 01h, indicating a write failure. the configuration of the writeblo ck function is straightforward. the blockid of the flash block, where the data is stored, must be determined and stored at sram address fah. table 9-2. srom function parameters variable name sram address key1/counter/return code 0,f8h key2/tmp 0,f9h blockid 0,fah pointer 0,fbh clock 0,fch mode 0,fdh delay 0,feh pcl 0,ffh table 9-3. srom return codes return code description 00h success 01h function not allowed due to level of protection on block. 02h software reset witho ut hardware reset. 03h fatal error, srom halted. table 9-4. readblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed. blockid 0,fah flash block number pointer 0,fbh first of 64 addresses in sram where returned data must be stored
cy7c63310 cy7c638xx document 38-08035 rev. *i page 15 of 74 the sram address of the first of the 64 bytes to be stored in flash must be indicated using the pointer variable in the parameter block (sram address fbh). finally, the clock and delay value must be set correctly. the clock value determines the length of the wr ite pulse that will be used to store the data in the flash. t he clock and delay values are dependent on the cpu speed and must be set correctly. 9.5.4 eraseblock function the eraseblock function is used to erase a block of 64 contiguous bytes in flash. the first thing the eraseblock function does is to check the protection bits and determine if the desired blockid is writable. if write protection is turned on, the eraseblock function will exit setting the accumulator and key2 back to 00h. key1 will have a value of 01h, indicating a write failure. the eraseblock function is only useful as the first step in programming. erasing a block will not cause data in a block to be one hundred percent unreadable. if the objective is to obliterate data in a block, the best method is to perform an eraseblock followed by a writeblock of all zeros. to set up the parameter block for the eraseblock function, correct key values must be stored in key1 and key2. the block number to be erased must be stored in the blockid variable and the clock and delay values must be set based on the current cpu speed. 9.5.5 protectblock function the encore ii devices offer flash protection on a block-by- block basis. table 9-7 lists the protection modes available. in the table, er and ew are used to indicate the ability to perform external reads and writes. for internal writes, iw is used. internal reading is always permitted by way of the romx instruction. the ability to read by way of the srom readblock function is indicated by sr. the protection level is stored in two bits according to table 9-7 . these bits are bit packed into the 64 bytes of the protection bl ock. therefore, each protection block byte stores the protection level for four flash blocks. the bits are packed into a byte, with the lowest numbered block?s protection level stored in the lowest numbered bits table 9-7 . the first address of the protection block contains the protection level for blocks 0 through 3; the second address is for blocks 4 through 7. the 64t h byte will store the protection level for blocks 252 through 255. the level of protection is only decreased by an eraseall, which places zeros in all locations of the protection block. to set the level of protection, the protec tblock function is used. this function takes data from sram, starting at address 80h, and ors it with the current values in the protection block. the result of the or operation is then stored in the protection block. the eraseblock function does not change the protection level for a block. because the sram location for the protection data is fixed and there is only one protection block per flash macro, the protectblock function expects very few variables in the para meter block to be set prior to calling the function. the parameter block va lues that must be set, besides the keys, are the clock and delay values. 9.5.6 eraseall function the eraseall function performs a series of steps that destroy the user data in the flash macros and resets the protection block in each flash macro to all zeros (the unprotected state). the eraseall function does not affect the three hidden blocks above the protection block, in each flash macro. the first of these four hidden blocks is us ed to store the protection table for its eight kbytes of user data. table 9-5. writeblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed. blockid 0,fah 8kb flash block number (00h?7fh) 4kb flash block number (00h?3fh) 3kb flash block number (00h?2fh) pointer 0,fbh first of 64 addresses in sram, where the data to be stored in flash is located prior to calling writeblock. clock 0,fch clock divider used to set the write pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h table 9-6. eraseblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value, when ssc is executed. blockid 0,fah flash block number (00h?7fh) clock 0,fch clock divider used to set the erase pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h table 9-7. protection modes mode settings descr iption marketing 00b sr er ew iw unprotected unprotected 01b sr er ew iw read protect factory upgrade 10b sr er ew iw disable external write field upgrade 11b sr er ew iw disable internal write full protection 76543210 block n+3 block n+2 block n+1 block n table 9-8. protectblock parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. clock 0,fch clock divider used to set the write pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h
cy7c63310 cy7c638xx document 38-08035 rev. *i page 16 of 74 the eraseall function begins by erasing the user space of the flash macro with the highest address range. a bulk program of all zeros is then performed on the same flash macro, to destroy all traces of the prev ious contents. the bulk program is followed by a second erase that leaves the flash macro in a state ready for writing. the erase, program, erase sequence is then performed on the next lowest flash macro in the address space if it exists. following the erase of the user space, the protection block for the flash macro with the highest address range is erased. following the erase of the protection block, zeros are written into every bit of the protection table. the next lowe st flash macro in the address space then has its protecti on block erased and filled with zeros. the end result of the eraseall fu nction is that all user data in the flash is destroyed and the flash is left in an unpro- grammed state, ready to accept one of the various write commands. the protection bits for all user data are also reset to the zero state the parameter block values that must be set, besides the keys, are the clock and delay values. 9.5.7 tableread function the tableread function gives t he user access to part-specific data stored in the flash during manufacturing. it also returns a revision id for the die (not to be confused with the silicon id). the table space for the encore ii is simply a 64-byte row broken up into eight tables of eight bytes. the tables are numbered zero through seven. all user and hidden blocks in the cy7c638xx parts consist of 64 bytes. an internal table holds the silicon id and returns the revision id. the silicon id is returned in sram, while the revision id is returned in the cpu_a and cpu_x registers. the silicon id is a value placed in the table by programming the flash and is controlled by cypress semiconductor product engineering. the revision id is hard coded into the srom. the revision id is discussed in more detail later in this section. an internal table holds alternate trim values for the device and returns a one-byte internal revision counter. the internal revision counter starts out with a value of zero and is incre- mented each time one of the other revision numbers is not incremented. it is reset to zero each time one of the other revision numbers is incremented. the internal revision count is returned in the cpu_a regi ster. the cpu_x register will always be set to ffh when trim values are read. the blockid value, in the parameter block, is used to indicate which table should be returned to the user. only the three least significant bits of the blockid parameter are used by tableread function for the cy7c638xx. the upper five bits are ignored. when the function is called, it transfers bytes from the table to sram addresses f8h?ffh. the m8c?s a and x registers are used by the tableread function to return the die?s revision id. the revision id is a 16-bit value hard coded into t he srom that uniquely identifies the die?s design. 9.5.8 checksum function the checksum function calculat es a 16-bit checksum over a user specifiable number of blo cks, within a single flash macro (bank) starting from block zero. the blockid parameter is used to pass in the number of blocks to calculate the checksum over. a blockid valu e of 1 will calculate the checksum of only block 0, while a blockid value of 0 will calculate the checksum of all 256 user blocks. the 16-bit checksum is returned in key1 and key2. the parameter key1 holds the lower eight bi ts of the checksum and the parameter key2 holds the upper eight bits of the checksum. the checksum algorithm executes the following sequence of three instructions over the num ber of blocks times 64 to be checksummed. romx add [key1], a adc [key2], 0 table 9-9. eraseall parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. clock 0,fch clock divider used to set the write pulse width. delay 0,feh for a cpu speed of 12 mhz set to 56h table 9-10. table read parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. blockid 0,fah table number to read. table 9-11. checksum parameters name address description key1 0,f8h 3ah key2 0,f9h stack pointer value when ssc is executed. blockid 0,fah number of flash blocks to calculate checksum on.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 17 of 74 10.0 clocking the encore ii internal oscillator outputs two frequencies, the internal 24 mhz oscillator and the 32 khz low-power oscil- lator. the internal 24 mhz oscillator is designed such that it may be trimmed to an output frequency of 24 mhz over temperature and voltage variation. with the presence of usb traffic, the internal 24 mhz oscillator can be set to precisely tune to usb timing requirements (24 mhz 1.5%). without usb traffic, the internal 24 mhz oscillator accuracy is 24 mhz 5% (between 0?70c). no external components are required to achieve this level of accuracy. the internal low-speed oscillator of nominally 32 khz provides a slow clock source for the encore ii in suspend mode, partic- ularly to generate a periodic wake-up interrupt and also to provide a clock to sequential logic during power-up and power- down events when the main clock is stopped. in addition, this oscillator can also be used as a clocking source for the interval timer clock (itmrclk) and capture timer clock (tcapclk). the 32 khz low-power oscillator can operate in low-power mode or can provide a more accurate clock in normal mode. the internal 32 khz low-power oscillator accuracy ranges (between 0?70 c) as follows: 5v normal mode: ?8% to + 16% 5v lp mode: +12% to + 48% 3.3v normal mode: ?10% to + 8% 3.3v lp mode: +4% to 35% when using the 32 khz oscillator the pitmrl/h registers must be read until 2 consecutive readings match before sending/receiving data. the following firmware example assumes the developer is interested in the lower byte of the pit. read_pit_counter: mov a, reg[pitmrl] mov [57h], a mov a, reg[pitmrl] mov [58h], a mov [59h], a mov a, reg[pitmrl] mov [60h], a ;;;start comparison mov a, [60h] mov x, [59h] sub a, [59h] jz done mov a, [59h] mov x, [58h] sub a, [58h] jz done mov x, [57h] ;;;correct data is in memory location 57h done: mov [57h], x ret
cy7c63310 cy7c638xx document 38-08035 rev. *i page 18 of 74 figure 10-1. clock block diagram cpu_clk ext 24 mhz mux clk_usb sel scale clk_24mhz clk_ext cpuclk sel mux scale (divide by 2 n , n = 0-5,7) clk_32 khz lp osc 32 khz sel scale out 0x 12 mhz 0x 12 mhz 1 1 ext/2 11 ext
cy7c63310 cy7c638xx document 38-08035 rev. *i page 19 of 74 10.1 clock architecture description the encore ii clock selection circuitry allows the selection of independent clocks for the cpu, usb, interval timers and capture timers. the cpu clock, cpuclk, can be sourced from an external clock or the internal 24 mhz oscillator. the selected clock source can optionally be divided by 2 n where n is 0-5,7 (see table 10-4 ). usbclk, which must be 12 mhz for the usb sie to function properly, can be sourced by the internal 24 mhz oscillator or an external 12 mhz/24 mhz clock. an optional divide by two allows the use of 24 mhz source. the interval timer clock (itmrclk), can be sourced from an external clock, the internal 24 mhz oscillator, the internal 32 khz low-power oscillator, or from the timer capture clock (tcapclk). a programmable prescaler of 1, 2, 3, 4 then divides the selected source. the timer capture clock (tcapclk) can be sourced from an external clock, internal 24 mhz oscillator, or the internal 32 khz low-power oscillator. the clkout pin (p0.1) can be driven from one of many sources. this is used for test and can also be used in some applications. the sources that can drive the clkout are: ? clkin after the optional eftb filter ? internal 24 mhz oscillator ? internal 32 khz low-power oscillator ? cpuclk after the programmable divider table 10-1. iosc trim (iosctr) [0x34] [r/w] bit # 7 6 5 4 3 2 1 0 field foffset[2:0] gain[4:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 d d d d d the iosc calibrate register is used to calibrate the internal o scillator. the reset value is undefined but during boot the srom writes a calibration value that is determi ned during manufacturing test. this value s hould not require change during normal use . this is the meaning of ?d? in the default field bit [7:5]: foffset [2:0] this value is used to trim the frequency of the internal oscillator. these bits ar e not used in factory calibration and will be zero. setting each of these bits causes the appr opriate fine offset in oscillator frequency. foffset bit 0 = 7.5 khz foffset bit 1 = 15 khz foffset bit 2 = 30 khz bit [4:0]: gain [4:0] the effective frequency change of the offset input is controlled through the gain input. a lower value of the gain setting incr eases the gain of the offset input. this val ue sets the size of each offset step for th e internal oscillator. nominal gain change (khz/offsetstep) at each bit, typi cal conditions (24 mhz operation): gain bit 0 = ?1.5 khz gain bit 1 = ?3.0 khz gain bit 2 = ?6 khz gain bit 3 = ?12 khz gain bit 4 = ?24 khz
cy7c63310 cy7c638xx document 38-08035 rev. *i page 20 of 74 table 10-2. lposc trim (lposctr) [0x36] [r/w] bit # 7 6 5 4 3 2 1 0 field 32-khz low power reserved 32-khz bias trim [1:0] 32-khz freq trim [3:0] read/write r/w ? r/w r/w r/w r/w r/w r/w default 0 d d d dd d d this register is used to calibrate the 32 khz low-speed oscilla tor. the reset value is undefined but during boot the srom write s a calibration value that is determined du ring manufacturing test. this value should not require change during normal use. this is the meaning of ?d? in the default field. if the 32 khz low-power bit needs to be written, care must be taken not to disturb the 32 khz bias trim and the 32 khz freq trim fields from their factory calibrated values bit 7: 32 khz low power 0 = the 32 khz low-speed oscillator operates in normal mode 1 = the 32 khz low-speed oscillator operates in a low-power mode. the oscillator continues to function normally but with reduced accuracy bit 6: reserved bit [5:4]: 32 khz bias trim [1:0] these bits control the bias curre nt of the low-power oscillator. 0 0 = mid bias 0 1 = high bias 1 0 = reserved 1 1 = reserved important note: do not program the 32 khz bias trim [1:0] field with the reserved 10b value as the oscillator does not oscillate at all corner conditions with this setting bit [3:0]: 32 khz freq trim [3:0] these bits are used to trim the fr equency of the low-power oscillator table 10-3. cpu/usb clock config ( cpuclkcr) [0x30] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved usb clk/2 disable usb clk select reserved cpuclk select read/write ? r/w r/w ? ? ? ? r/w default 0 0 0 0 0 0 0 0 bit 7: reserved bit 6: usb clk/2 disable this bit only affects the usbclk when the source is the external crystal oscillator. when the usbclk source is the internal 24 mhz oscillator, the divide by two is always enabled 0 = usbclk source is divided by two. this is the correct setti ng to use when the internal 24 mhz oscillator is used, or when the external source is used with a 24 mhz clock 1 = usbclk is undivided. use this setting only with a 12 mhz external clock bit 5: usb clk select this bit controls the clock source for the usb sie 0 = internal 24 mhz oscillator. with the presence of usb traffic, the internal 24 mhz oscillator can be trimmed to meet the usb requirement of 1.5% tolerance (see table 10-5 ) 1 = external clock?internal oscillator is not trimmed to usb traffic. proper usb sie operation requires a 12 mhz or 24 mhz clock accurate to <1.5%. bit [4:1]: reserved bit 0: cpu clk select 0 = internal 24 mhz oscillator. 1 = external clock?external clock at clkin (p0.0) pin. note: the cpu speed selection is confi gured using the osc_cr0 register ( table 10-4 )
cy7c63310 cy7c638xx document 38-08035 rev. *i page 21 of 74 table 10-4. osc control 0 (osc_cr0) [0x1e0] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved no buzz sleep timer [1:0] cpu speed [2:0] read/write ? ? r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit [7:6]: reserved bit 5: no buzz during sleep (the sleep bit is set in the cpu_scr register? table 11-1 ), the lvd and por detection circuit is turned on periodically to detect any por and lvd events on the v cc pin (the sleep duty cycle bits in the eco_tr are used to control the duty cycle? table 13-3 ). to facilitate the detection of por and lvd ev ents, the no buzz bit is used to force the lvd and por detection circuit to be continuously enabled during sleep. this results in a faster response to an lvd or por event during sleep at the expense of a slight ly higher than average sleep current 0 = the lvd and por detection circuit is turned on pe riodically as configured in the sleep duty cycle 1 = the sleep duty cycle value is overridden. the lvd and por detection circuit is always enabled note: the periodic sleep duty cycle enabling is independent with the sleep interval shown in the sleep [1:0] bits below bit [4:3]: sleep timer [1:0] note: sleep intervals are approximate bit [2:0]: cpu speed [2:0] the encore ii may operate over a range of cpu clock speeds. the reset value for the cpu speed bits is ze ro; therefore, the default cpu speed is one-eighth of the internal 24 mhz, or 3 mhz regardless of the cpu speed bit?s setting, if the actual cpu sp eed is greater than 12 mhz, t he 24 mhz operating requirements apply. an example of this scenario is a dev ice that is configured to use an external clock, which is supplying a frequency of 2 0 mhz. if the cpu speed register?s value is 0b011, the cpu clock will be 20 mhz. ther efore the supply voltage requirements for the device are the same as if the part was operating at 24 mhz. the operating voltage requirements are not relaxed until the cpu speed is at 12 mhz or less important note: correct usb operations require the cpu clock speed be at least 1.5 mhz or not less than usb clock/8. if the two clocks have the same source th en the cpu clock divider should no t be set to divide by more than 8. if the two clocks have different sources, care must be taken to ensure that the maximum ratio of usb clock/cpu clock can never exceed 8 across the full specification range of both clock sources sleep timer [1:0] sleep timer clock frequency (nominal) sleep period (nominal) watchdog period (nominal) 00 512 hz 1.95 ms 6 ms 01 64 hz 15.6 ms 47 ms 10 8 hz 125 ms 375 ms 11 1 hz 1 sec 3 sec cpu speed [2:0] cpu when internal oscillator is selected external clock 000 3 mhz (default) clock in/8 001 6 mhz clock in/4 010 12 mhz clock in/2 011 24 mhz clock in/1 100 1.5 mhz clock in/16 101 750 khz clock in/32 110 187 khz clock in/128 111 reserved reserved
cy7c63310 cy7c638xx document 38-08035 rev. *i page 22 of 74 10.1.1 interval timer clock (itmrclk) the interval timer clock (titmrclk), can be sourced from an external clock, the internal 24 mhz oscillator, the internal 32-khz low-power oscillator, or the timer capture clock. a programmable prescaler of 1, 2, 3 or 4 then divides the selected source. the 12-bit pr ogrammable interval timer is a simple down counter with a programmable reload value. it provides a 1 s resolution by default. when the down counter reaches zero, the next clock is spent reloading. the reload value can be read and written while the counter is running, but care must be taken to ensure that the counter does not unintentionally reload while the 12-bit reload value is only partially stored?i.e., between the two writes of the 12-bit value. the programmable interval timer generates an interrupt to the cpu on each reload. the parameters to be set will show up on the device editor view of psoc designer once you place the encore ii timer user module. the parameters are pitimer_source and pitimer_divider. the pitimer_source is the clock to the timer and the pitmer_divider is the value the clock is divided by. table 10-5. usb osclo ck clock configuration (o sclckcr) [0x39] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved fine tune only usb osclock disable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 0 0 0 0 this register is used to trim the internal 24 mhz oscillator using received low-speed usb packets as a timing reference. the usb osclock circuit is active when the internal 24 mhz oscillator provides the usb clock bit [7:2]: reserved bit 1: fine tune only 0 = enable 1 = disable the oscillator lock from performing the coarse-tune portion of its retuning. the oscillator lock must be allowed to perform a coarse tuning in order to tune the oscillator for corre ct usb sie operation. after the oscillator is properly tuned t his bit can be set to reduce variance in the internal oscillator frequency th at would be caused course tuning bit 0: usb osclock disable 0 = enable. with the presence of usb traffic, the inte rnal 24 mhz oscillator precisely tunes to 24 mhz 1.5% 1 = disable. the internal 24 mhz oscillator is not trimmed bas ed on usb packets. this setting is useful when the internal oscillator is not sour cing the usbsie clock table 10-6. timer clock co nfig (tmrclkcr) [0x31] [r/w] bit # 7 6 5 4 3 2 1 0 field tcapclk divider tcapclk select itmrclk divider itmrclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 1 1 1 1 bit [7:6]: tcapclk divider [1:0] tcapclk divider controls the tcapclk divisor 0 0 = divider value 2 0 1 = divider value 4 1 0 = divider value 6 1 1 = divider value 8 bit [5:4]: tcapclk select the tcapclk select field controls the source of the tcapclk 0 0 = internal 24 mhz oscillator 0 1 = external clock?external clock at clkin (p0.0) input. 1 0 = internal 32-khz low-power oscillator 1 1 = tcapclk disabled note: the 1024- s interval timer is based on the assumption that tcapclk is running at 4 mhz. changes in tcapclk frequency will cause a corresponding change in the 1024- s interval timer frequency bit [3:2]: itmrclk divider itmrclk divider controls the itmrclk divisor. 0 0 = divider value of 1 0 1 = divider value of 2 1 0 = divider value of 3 1 1 = divider value of 4 bit [1:0]: itmrclk select 0 0 = internal 24 mhz oscillator 0 1 = external clock?external clock at clkin (p0.0) input. 1 0 = internal 32-khz low-power oscillator 1 1 = tcapclk
cy7c63310 cy7c638xx document 38-08035 rev. *i page 23 of 74 the interval register (pitmr) holds the value that is loaded into the pit counter on terminal count. the pit counter is a down counter. the programmable interval timer resolution is configurable. for example: tcapclk divide by x of cpu clock (for example tcapclk divide by 2 of a 24 mhz cpu clock will give a frequency of 12 mhz) itmrclk divide by x of tcapclk (for example, itmrclk divide by 3 of tcapclk is 4 mhz so resolution is 0.25 s) 10.1.2 timer capture clock (tcapclk) the timer capture clock can be sourced from an external clock, internal 24 mhz oscillat or or the internal 32-khz low- power oscillator. a programmable pre-scaler of 2, 4, 6, or 8 then divides the selected source. figure 10-2. programmable in terval timer block diagram system clock clock timer configuration status and control 12-bit reload value 12-bit down counter 12-bit reload counter interrupt c ontroller
cy7c63310 cy7c638xx document 38-08035 rev. *i page 24 of 74 10.2 cpu clock during sleep mode when the cpu enters sleep mode the cpuclk select (bit [0], table 10-3 ) is forced to the internal oscillator, and the oscil- lator is stopped. when the cpu comes out of sleep mode it is running on the internal oscillator. the internal oscillator recovery time is three clock cycl es of the internal 32-khz low- power oscillator. if the system requires the cpu to run off the external clock after awaking from sleep mode, firmware will need to switch the clock source for the cpu. 11.0 reset the microcontroller supports two types of resets: power-on reset (por) and watchdog re set (wdr). when reset is initiated, all registers are restor ed to their default states and all interrupts are disabled. the occurrence of a reset is recorded in the system status and control register (cpu_scr). bits within this register record the occurrence of por and wdr reset respectively. the firmware can interrogate these bits to determine the cause of a reset. the microcontroller resumes ex ecution from flash address 0x0000 after a reset. the internal clocking mode is active after a reset, until changed by user firmware. note the cpu clock defaults to 3 mhz (internal 24 mhz oscil- lator divide-by-8 mode) at por to guarantee operation at the low v cc that might be present during the supply ramp. figure 10-3. timer capture block diagram 16-bit counter configuration status and control prescale mux capture registers interrupt controller 1ms timer overflow interrupt captimer clock system clock capture0 int capture1 in t table 10-7. clock i/o config (clkiocr) [0x32] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved clkout select read/write ? ? ?--- r/w r/w default 0 0 0000 0 0 bit [7:2]: reserved bit [1:0]: clkout select 0 0 = internal 24 mhz oscillator 0 1 = external clock ? external clock at clkin (p0.0) 1 0 = internal 32-khz low-power oscillator 1 1 = cpuclk
cy7c63310 cy7c638xx document 38-08035 rev. *i page 25 of 74 11.1 power-on reset por occurs every time the power to the device is switched on. por is released when the supply is typically 2.6v for the upward supply transition, with typically 50 mv of hysteresis during the power-on transient. bit 4 of the system status and control register (cpu_scr) is set to record this event (the register contents are set to 00010000 by the por). after a por, the microprocessor is held off for approximately 20 ms for the v cc supply to stabilize before executing the first instruction at address 0x00 in the flash. if the v cc voltage drops below the por downward supply trip point, por is reasserted. the v cc supply needs to ramp linearly from 0 to 4v in less than 200 ms. important : the pors status bit is set at por and can only be cleared by the user. it cannot be set by firmware. 11.2 watchdog timer reset the user has the option to enable the wdt. the wdt is enabled by clearing the pors bit. once the pors bit is cleared, the wdt cannot be disabled. the only exception to this is if a por event takes place, which will disable the wdt. the sleep timer is used to generate the sleep time period and the watchdog time period. the sleep timer uses the internal 32-khz low-power oscillator system clock to produce the sleep time period. the user can program the sleep time period using the sleep timer bits of the osc_cr0 register ( table 10-4 ). when the sleep time elapses (sleep timer overflows), an interrupt to the sleep timer interrupt vector will be generated. the watchdog timer period is automatically set to be three counts of the sleep timer overflows. this represents between two and three sleep intervals depending on the count in the sleep timer at the previous wdt clear. when this timer reaches three, a wdr is generated. the user can either clear the wdt, or the wdt and the sleep timer. whenever the user writ es to the reset wdt register (res_wdt), the wdt will be cleared. if the data that is written is the hex value 0x38, the sleep timer will also be cleared at the same time. table 11-1. system status and control register (cpu_scr) [0xff] [r/w] bit # 7 6 5 4 3 2 1 0 field gies reserved wdrs pors sleep reserved stop read/write r ? r/c [4] r/c [4] r/w ? ? r/w default 0 0 0 1 00 0 0 the bits of the cpu_scr register are used to convey status and control of events for various functions of an encore ii device bit 7: gies the global interrupt enable status bit is a read only status bit and its use is discouraged. the gies bit is a legacy bit, whic h was used to provide the ability to read the gie bit of the cpu_ f register. however, the cpu_f r egister is now readable. when this bit is set, it indica tes that the gie bit in the cpu_f register is also set which, in turn, indicates that the microproces sor will service interrupts 0 = global interrupts disabled 1 = global interrupt enabled bit 6: reserved bit 5: wdrs the wdrs bit is set by the cpu to indicate that a wdr event has occurred. the user ca n read this bit to determine the type of reset that has occurred. the user can clear but not set this bit 0 = no wdr 1 = a wdr event has occurred bit 4: pors the pors bit is set by the cpu to indicate that a por event has occurred. the user can read this bit to determine the type of reset that has occurred. the user can clear but not set this bit 0 = no por 1 = a por event has occurred. (note that wdr events will not occur until this bit is cleared) bit 3: sleep set by the user to enable cpu sleep state. cpu will remain in sleep mode until any interrupt is pending. the sleep bit is cover ed in more detail in the sleep mode section 0 = normal operation 1 = sleep bit [2:1]: reserved bit 0: stop this bit is set by the user to halt the cpu. the cpu will rema in halted until a reset (wdr, por, or external reset) has taken place. if an application wants to stop co de execution until a reset, the preferred meth od would be to use the halt instruction rather than writing to this bit 0 = normal cpu operation 1 = cpu is halted (not recommended) note 4. c = clear. this bit can only be cleared by the user and cannot be set by firmware.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 26 of 74 12.0 sleep mode the cpu can only be put to sleep by the firmware. this is accomplished by setting the sleep bit in the system status and control register (cpu_scr). this stops the cpu from executing instructions, and the cpu will remain asleep until an interrupt comes pending, or there is a reset event (either a power-on reset, or a watchdog timer reset). the low-voltage detection circuit (lvd) drops into fully functional power-reduced states, and the latency for the lvd is increased. the actual lat ency can be traded against power consumption by changing sleep duty cycle field of the eco_tr register. the internal 32 khz low-speed oscillator remains running. prior to entering suspend mode, firmware can optionally configure the 32 khz low-speed osc illator to operate in a low- power mode to help reduce the over all power consumption (using bit 7, table 10-2 ). this will help save approximately 5 a; however, the trade off is that the 32 khz low-speed oscillator will be less accurate. all interrupts remain active. only the occurrence of an interrupt will wake the part from sleep. t he stop bit in the system status and control register (cpu_scr) must be cleared for a part to resume out of sleep. the global interrupt enable bit of the cpu flags register (cpu_f) does not have any effect. any unmasked interrupt will wake th e system up. as a result, any interrupts not intended for waking must be disabled through the interrupt mask registers. when the cpu enters sleep mode th e cpuclk select (bit 1, table 10-3 ) is forced to the intern al oscillator. the internal oscillator recovery time is thre e clock cycles of the internal 32 khz low-power oscillator. the internal 24 mhz oscillator restarts immediately on exiting sleep mode. if an external clock is used, firmware will need to switch the clock source for the cpu. on exiting sleep mode, once the clock is stable and the delay time has expired, the instruction immediately following the sleep instruction is executed before the interrupt service routine (if enabled). the sleep interrupt allows the microcontroller to wake up periodically and poll system components while maintaining very low average power consumption. the sleep interrupt may also be used to provide periodic interrupts during non- sleep modes. 12.1 sleep sequence the sleep bit is an input into the sleep logic circuit. this circuit is designed to sequence the device into and out of the hardware sleep state. the hardware sequence to put the device to sleep is shown in figure 12-1 and is defined as follows. 1.firmware sets the sleep bit in the cpu_scr0 register. the bus request (brq) signal to the cpu is immediately asserted. this is a reques t by the system to halt cpu operation at an instruction boundary. the cpu samples brq on the positive edge of cpuclk. 2.due to the specific timing of the register write, the cpu issues a bus request acknowledge (bra) on the following positive edge of the cpu clock. the sleep logic waits for the following negative edge of the cpu clock and then asserts a system-wide power down (pd) signal. in figure 12-1 the cpu is halted and the syste m-wide power down si gnal is asserted. 3. the system-wide pd (power down) signal controls several major circuit blocks: the flash memory module, the internal 24 mhz oscillator, the eftb filter and the bandgap voltage reference. these circuits transition into a zero power state. the only operational circuits on chip are the low power oscil- lator, the bandgap refresh circuit, and the supply voltage monitor (por/lvd) circuit. note: to achieve the lowest possible power consumption during suspend/sleep, the following conditions must be observed in addition to considerations for the sleep timer: ? all gpios must be set to outputs and driven low ? the usb pins p1.0 and p1.1 should be configured as inputs with their pull-ups enabled. table 11-2. reset watchdog timer (reswdt) [0xe3] [w] bit # 7 6 5 4 3 2 1 0 field reset watchdog timer [7:0] read/write w w w w ww w w default 0 0 0 0 00 0 0 any write to this register will clear watchdog timer, a write of 0x38 will also clear the sleep timer bit [7:0]: reset watchdog timer [7:0]
cy7c63310 cy7c638xx document 38-08035 rev. *i page 27 of 74 figure 12-1. sleep timing 12.2 wake up sequence once asleep, the only event that can wake the system up is an interrupt. the global interrupt enable of the cpu flag register does not need to be set. any unmasked interrupt will wake the system up. it is optional for the cpu to actually take the interrupt after the wake up sequence. the wake up sequence is synchronized to the 32 khz clock for purposes of sequencing a startup delay, to allow the flash memory module enough time to power up before the cpu asserts the first read access. another reason for the de lay is to allow the oscillator, bandgap, and lvd/por circuits time to settle before actually being used in the system. as shown in figure 12-2 , the wake up sequence is as follows: 1.the wake up interrupt occurs and is synchronized by the negative edge of the 32 khz clock. 2.at the following pos itive edge of the 32 khz clock, the system wide pd signal is negated. the flash memory module, internal oscillator, eftb, and bandgap circuit are all powered up to a normal operating state. 3.at the following positive edge of the 32 khz clock, the current values for the precision por and lvd have settled and are sampled. 4.at the following negative edge of the 32 khz clock (after about 15 s nominal), the brq signal is negated by the sleep logic circuit. on the following cpuclk, bra is negated by the cpu and instruction execution resumes. note that in figure 12-2 fixed function blocks, such as flash, internal oscil- lator, eftb, and bandgap, have about 15 sec start up. the wake-up times (interrupt to cpu operational) will range from 75 s to 105 s. firmware write to scr sleep bit causes an immediate brq iow sleep brq pd bra cpuclk cpu captures brq on next cpuclk edge cpu responds with a bra on the falling edge of cpuclk, pd is asserted. the 24/48 mhz system clock is halted; the flash and bandgap are powered down
cy7c63310 cy7c638xx document 38-08035 rev. *i page 28 of 74 figure 12-2. wake up timing int sleep pd lvd ppor bandgap clk32k sample sample lvd/por cpuclk/ 24mhz bra brq enable cpu (not to scale) sleep timer or gpio interrupt occurs interrupt is double sampled by 32k clock and pd is negated to system cpu is restarted after 90ms (nominal)
cy7c63310 cy7c638xx document 38-08035 rev. *i page 29 of 74 13.0 low-voltage detect control table 13-1. low-voltage control register (lvdcr) [0x1e3] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved porlev[1:0] reserved vm[2:0] read/write ? ? r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the configuration of the power-on reset/low-voltage detection block bit [7:6]: reserved bit [5:4]: porlev[1:0] this field controls the level below which the precision power-on-reset (ppor) detector generates a reset 0 0 = 2.7v range (trip near 2.6v) 0 1 = 3v range (trip near 2.9v) 1 0 = 5v range, > 4.75v (trip near 4.65v) 1 1 = ppor will not generate a reset, but values read from the voltage monitor comparators register ( table 13-2 ) give the internal ppor comparator state with tr ip point set to the 3v range setting bit 3: reserved bit [2:0]: vm[2:0] this field controls the level below which the low-voltage-dete ct trips?possibly generating an in terrupt and the level at which the flash is enabled for operation. vm[2:0] lvd trip point (v) min lvd trip point (v) typ lvd trip point (v) max 000 2.681 2.70 2.735 001 2.892 2.92 2.950 010 2.991 3.02 3.053 011 3.102 3.13 3.164 100 4.439 4.48 4.528 101 4.597 4.64 4.689 110 4.680 4.73 4.774 111 4.766 4.82 4.862 table 13-2. voltage monitor comparat ors register (vltcmp) [0x1e4] [r] bit # 7 6 5 4 3 2 1 0 field reserved lvd ppor read/write ? ? ? ? ?? r r default 0 0 0 0 00 0 0 this read-only register allows reading t he current state of the low-voltage-detec tion and precision-power-on-reset compar- ators bit [7:2]: reserved bit 1: lvd this bit is set to indicate that the low-voltage-detect comp arator has tripped, indicating t hat the supply voltage has gone bel ow the trip point set by vm[2:0] (see table 13-1 ) 0 = no low-voltage-detect event 1 = a low-voltage-detect has tripped bit 0: ppor this bit is set to indicate that the precision-power-on-reset co mparator has tripped, indicating that the supply voltage is bel ow the trip point set by porlev[1:0] 0 = no precision-power-on-reset event 1 = a precision-power-on-reset event has occurred note: this register can only be accessed in the second bank of i/o space. this requires setting the xio bit in the cpu flags register.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 30 of 74 13.0.1 eco trim register 14.0 general-purpose i/o ports 14.1 port data registers table 13-3. eco (eco_tr) [0x1eb] [r/w] bit # 7 6 5 4 3 2 1 0 field sleep duty cycle [1:0] reserved read/write r/w r/w ? ? ? ? ? ? default 0 0 0 0 00 0 0 this register controls the ratios (in numb ers of 32-khz clock periods) of ?on? time versus ?off? time for lvd and por detection circuit bit [7:6]: sleep duty cycle [1:0] 0 0 = 128 periods of the inter nal 32 khz low-speed oscillator 0 1 = 512 periods of the inter nal 32 khz low-speed oscillator 1 0 = 32 periods of the internal 32 khz low-speed oscillator 1 1 = 8 periods of the internal 32 khz low-speed oscillator table 14-1. p0 data regi ster (p0data)[0x00] [r/w] bit # 7 6 5 4 3 2 1 0 field p0.7 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1/clkout p0.0/clkin read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this register contains the data for port 0. writing to this r egister sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 0 pins. bit 7: p0.7 data p0.7 only exists in the cy7c638xx bit [6:5]: p0.6?p0.5 data/tio1 and tio0 beside their use as the p0.6?p0.5 gpios, these pins can also be used for the alternate functions as the capture timer input or timer output pins (tio1 and tio0 ). to configure the p0.5 and p0.6 pins, refer to the p0.5/tio0?p0.6/tio1 configuration register ( table 14-8 ) the use of the pins as the p0.6?p0.5 gpios and the al ternate functions exist in all the encore ii parts bit [4:2]: p0.4?p0.2 data/int2 ? int0 beside their use as the p0.4?p0.2 gpios, these pins can also be used for the alte rnate functions as the interrupt pins (int0?int2). to configure the p0.4?p0.2 pins, refer to the p0.2/int0?p0.4/int2 configuration register ( table 14-7 ) the use of the pins as the p0.4?p0.2 gpios and the al ternate functions exist in all the encore ii parts bit 1: p0.1/clkout beside its use as the p0.1 gpio, this pin can also be used for the alternate function as the clk out pin. to configure the p0.1 pin, refer to the p0.1/clkout configuration register ( table 14-6 ) bit 0: p0.0/clkin beside its use as the p0.0 gpio, this pin can also be used for the alternate function as the clki n pin. to configure the p0.0 pin, refer to the p0.0/clkin configuration register ( ta ble 14 -5 )
cy7c63310 cy7c638xx document 38-08035 rev. *i page 31 of 74 14.2 gpio port configuration all the gpio configuration registers have common configu- ration controls. the following are the bit definitions of the gpio configuration registers 14.2.1 int enable when set, the int enable bit allows the gpio to generate inter- rupts. interrupt generate can o ccur regardless of whether the pin is configured for input or output. all interrupts are edge sensitive, however for any interrupt that is shared by multiple sources (i.e., ports 2, 3, and 4) all inputs must be deasserted before a new interrupt can occur. when clear, the corresponding interrupt is disabled on the pin. it is possible to configure gpios as outputs, enable the interrupt on the pin and then to generate the interrupt by driving the appropriate pin state. this is useful in test and may have value in applications as well. table 14-2. p1 data register (p1data) [0x01] [r/w] bit # 7 6 5 4 3 2 1 0 field p1.7 p1.6/smiso p1.5/smosi p1.4/sclk p1.3/ssel p1.2/vreg p1.1/d? p1.0/d+ read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 1. writing to this r egister sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 1 pins. bit 7: p1.7 data p1.7 only exists in the cy7c638xx bit [6:3]: p1.6?p1.3 data/spi pins (smiso, smosi, sclk, ssel) beside their use as the p1.6?p1.3 gpios, th ese pins can also be used for the alternate function as the spi interface pins. to configure the p1.6?p1.3 pins, refer to the p1.3?p1.6 configuration register ( table 14-13 ) the use of the pins as the p1.6?p1.3 gpios and the al ternate functions exist in all the encore ii parts. bit 2: p1.2/vreg on the cy7c638(2/3)3, this pin can be us ed as the p1.2 gpio or the vreg output . if the vreg output is enabled (bit 0 table 19-1 is set), a 3.3v source is placed on the pi n and the gpio function of the pin is disabled on the cy7c63813, this pin can only be used as the vreg output when usb mode is enabled. in non-usb mode, this pin can be used as the p1.2 gpio. the vreg functionality is no t present in the cy7c63310 and the cy7c63801 variants. a 1 f min, 2 f max capacitor is required on vreg output. bit [1:0]: p1.1?p1.0/d? and d+ when usb mode is disabled (bit 7 in table 21-1 is clear), the p1.1 and p1.0 bits are us ed to control the state of the p1.0 and p1.1 pins. when the usb mode is enabled, the p1.1 and p1.0 pi ns are used as the d? and d+ pins respectively. if the usb force state bit (bit 0 in table 18-1 ) is set, the state of the d? and d+ pins can be controlled by writing to the d? and d+ bits table 14-3. p2 data register (p2data) [0x02] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved p2.1?p2.0 read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 2. writing to this r egister sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 2 pins bit [7:2]: reserved data [7:2] bit [1:0]: p2 data [1:0] p2.1?p2.0 only exist in the cy7c638(2/3)3 table 14-4. p3 data register (p3data) [0x03] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved p3.1?p3.0 read/write - - - - - - r/w r/w default 0 0 0 0 0 0 0 0 this register contains the data for port 3. writing to this r egister sets the bit values to be output on output enabled pins. r eading from this register returns the current state of the port 3 pins bit [7:2]: reserved data [7:2] bit [1:0]: p3 data [1:0] p3.1?p3.0 only exist in the cy7c638(2/3)3
cy7c63310 cy7c638xx document 38-08035 rev. *i page 32 of 74 14.2.2 int act low when set, the corresponding interrupt is active on the falling edge. when clear, the corresponding interrupt is active on the rising edge. 14.2.3 ttl thresh when set, the input has ttl threshold. when clear, the input has standard cmos threshold. 14.2.4 high sink when set, the output can sink up to 50 ma. when clear, the output can sink up to 8 ma. on the cy7c638xx, only the p1.7 ?p1.3 have 50 ma sink drive capability. other pins have 8 ma sink drive capability. 14.2.5 open drain when set, the output on the pin is determined by the port data register. if the corresponding bit in the port data register is set, the pin is in high-impedance state. if the corresponding bit in the port data register is clear, the pin is driven low. when clear, the output is driven low or high. 14.2.6 pull up enable when set the pin has a 7k pull up to v cc (or vreg for ports with v3.3 enabled). when clear, the pull up is disabled. 14.2.7 output enable when set, the output driver of the pin is enabled. when clear, the output driv er of the pin is disabled. for pins with shared functions there are some special cases. 14.2.8 vreg output/spi use the p1.2(vreg), p1.3(ssel), p1.4(sclk), p1.5(smosi) and p1.6(smiso) pins can be used for their dedicated functions or for gpio. to enable the pin for gpio, clear the corresponding vreg output or spi use bit. the spi function controls the output enable for its dedicated function pins when their gpio enable bit is clear. the vreg output is not available on the cy7c63801 and cy7c63310. 14.2.9 3.3v drive the p1.3(ssel), p1.4(s clk), p1.5(smosi) and p1.6(smiso) pins have an alternate voltage source from the voltage regulator. if the 3.3v drive bit is set a high level is driven from the voltage regulator instead of from v cc . setting the 3.3v drive bit does not enable the voltage regulator. that must be done explicitly by setting the vreg enable bit in the vregcr register ( ta ble 19 -1 ). figure 14-1. block diagram of a gpio v cc vreg v cc vreg gpi o pi n r up data ou t v cc gnd vreg gnd 3.3v dri ve pul l -up enabl e output enabl e open drai n por t dat a hi gh si nk data in ttl threshol d
cy7c63310 cy7c638xx document 38-08035 rev. *i page 33 of 74 table 14-5. p0.0/clkin configuration (p00cr) [0x05] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write -- r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this pin is shared between the p0.0 gpio use and the clkin pin for an external clock. when the external clock input is enabled the settings of this register are ignored the use of the pin as the p0.0 gpio is available in all the encore ii parts. in the cy7c638xx, only 8 ma sink drive capability is avail able on this pin regardless of the setting of the high sink bit table 14-6. p0.1/clkout conf iguration (p01cr) [0x06] r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this pin is shared between the p0.1 gpio use and the clkout pi n. when clk output is set, the internally selected clock is sent out onto p0.1clkout pin. the use of the pin as the p0.1 gpio is av ailable in all the encore ii parts. in the cy7c638xx, only 8 ma sink drive capability is available on this pin regardless of the setting of the high sink bit bit 7: clk output 0 = the clock output is disabled 1 = the clock selected by the clk select field (bit [1:0] of the clkiocr register? table 10-7 ) is driven out to the pin table 14-7. p0.2/int0?p0.4/int2 config uration (p02cr?p04cr) [0x07?0x09] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int act low ttl thresh reserved open drain pull-up enable output enable read/write ? ? r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the operation of pi ns p0.2?p0.4 respectively. these pins ar e shared between the p0.2?p0.4 gpios and the int0?int2. these registers exist in all encore ii parts. the int0?int2 interrupts are different than all the other gpio interrupts. these pins are connected directly to the interrup t controller to provide three edge-sensitive interrupts with indep endent interrupt vectors. these interrupts occur on a rising edge when int act low is clear and on a falling edge when int act low is set. these pins are enabled as interrupt sources in the interrupt controller registers ( table 17-8 and table 17-6 ). to use these pins as interrupt inputs configure them as inputs by clearing the corresponding output enable. if the int0?int2 pins are configured as outputs with interrupts enabled, firmware c an generate an interrupt by writing the appropriate value to the p0.2, p0.3 and p0.4 data bits in the p0 data register regardless of whether the pins are used as interrupt or gpio pins the int enable, in t act low, ttl threshold, open drain, and pull-up enable bits control the behavior of the pin the p0.2/int0?p0.4/int2 pins are individually configured wi th the p02cr (0x07), p03cr (0x08), and p04cr (0x09) respec- tively. note: changing the state of the int act low bit can cause an unin tentional interrupt to be gener ated. when configuring these interrupt sources, it is best to follow the following procedure: 1. disable interrupt source 2. configure interrupt source 3. clear any pending interrupts from the source 4. enable interrupt source
cy7c63310 cy7c638xx document 38-08035 rev. *i page 34 of 74 table 14-8. p0.5/tio0 ? p0.6/tio1 config uration (p05cr?p06cr) [0x0a?0x0b] [r/w] bit # 7 6 5 4 3 2 1 0 field tio output int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the operation of pins p0.5 through p0 .6, respectively. these registers exist in all encore ii parts. p0.5 and p0.6 are shared with tio0 and tio1, respectively. to us e these pins as capture timer inputs, configure them as inputs by clearing the corresponding output enable. to use tio0 and t io1 as timer outputs, set the tiox output and output enable bits. if these pins are configured as outputs and the tio output bit is clear, firmware can control the tio0 and tio1 inputs by writing the value to the p0.5 and p0.6 data bits in the p0 data register regardless of whether either pin is used as a tio or gpio pin the int enable, int act low, ttl threshold, open drain, and pull- up enable control the behavior of the pin. tio0(p0.5) when enabled outputs a positive pulse from the 1024- s interval timer. this is the same signal that is used internally to generate the 1024- s timer interrupt. this signal is not gated by the interrupt enable state. tio1(p0.6) when enabled outputs a positive pulse from the progra mmable interval timer. this is the same signal that is used internally to generate the programmable timer interval interr upt. this signal is not gated by the interrupt enable state the p0.5/tio0 and p0.6/tio1 pins are individually config ured with the p05cr (0x0a) and p06cr (0x0b), respectively table 14-9. p0.7 configuration (p07cr) [0x0c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable read/write ? r/w r/w r/w ? r/w r/w r/w default 0 0 0 0 0 0 0 0 this register controls the opera tion of pin p0.7. the p0.7 pin only exists in the cy7c638(2/3)3 table 14-10. p1.0/d+ configuration (p10cr) [0x0d] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved ps/2 pull-up enable output enable read/write r/w r/w r/w ? ?? r/w r/w default 0 0 0 0 00 0 0 this register controls the opera tion of the p1.0 (d+) pin when the usb interface is not enabled, allowing the pin to be used as a ps2 interface or a gpio. see table 21-1 for information on enabling usb. when usb is enabled, none of the controls in this register have any affect on the p1.0 pin. note : the p1.0 is an open drain only output. it can actively driv e a signal low, but cannot actively drive a signal high. bit 1: ps/2 pull-up enable 0 = disable the 5k ohm pull-up resistors 1 = enable 5k ohm pull-up resistors for both p1.0 and p1.1. enabl e the use of the p1.0 (d+) and p1.1 (d?) pins as a ps2 style interface table 14-11. p1.1/d? configuration (p11cr) [0x0e] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low reserved open drain reserved output enable read/write ? r/w r/w ? ?r/w? r/w default 0 0 0 0 00 0 0 this register controls the opera tion of the p1.1 (d?) pin when the usb interfac e is not enabled, allowing the pin to be used as a ps2 interface or a gpio. see table 21-1 for information on enabling usb. when usb is enabled, none of the controls in this register have any affect on the p1.1 pin. when usb is disabled, the 5k ohm pull-up resistor on this pin can be enabled by the ps/2 pull-up enable bit of the p10cr register ( table 14-10 ) note : there is no 2 ma sourcing capability on this pin. the pin can only sink 5 ma at v ol3 ( section 26.0 )
cy7c63310 cy7c638xx document 38-08035 rev. *i page 35 of 74 table 14-12. p1.2 configuration (p12cr) [0x0f] [r/w] bit # 7 6 5 4 3 2 1 0 field clk output int enable int act low ttl threshold reserved open drain pull-up enable output enable read/write r/w r/w r/w r/w ?r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the operation of the p1.2 bit 7: clk output 0 = the internally selected clock is not sent out onto p1.2 pin 1 = when clk output is set, the internally selected clock is sent out onto p1.2 pin table 14-13. p1.3 configuration (p13cr) [0x10] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low 3.3v drive high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 this register controls the operati on of the p1.3 pin. this register exists in all encore ii parts the p1.3 gpio?s threshold is always set to ttl when the spi hardware is enabled, the output enable and output st ate of the pin is controlled by the spi circuitry. when the sp i hardware is disabled, the pin is controlled by the output enable bit and the corresponding bit in the p1 data register. regardless of whether the pin is used as an spi or gpio pin the int enable, int act low , 3.3v drive, high sink, open drain, and pull-up enable control the behavior of the pin the 50 ma sink drive capability is only available in the cy7c638xx. table 14-14. p1.4?p1.6 configuratio n (p14cr?p16cr) [0x11?0x13] [r/w] bit # 7 6 5 4 3 2 1 0 field spi use int enable int act low 3.3v drive high sink open drain pull-up enable output enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 these registers control the operation of pins p1.4?p1.6, respectively. these registers exist in all encore ii parts the p1.4?p1.6 gpio?s threshold is always set to ttl when the spi hardware is enabled, pins that are configured as spi use have their output enable and output state controlled by the spi circuitry. when the spi hardware is disabled or a pin has its spi use bit clear, the pin is controlled by the output en able bit and the corresponding bit in the p1 data register. regardless of whether any pin is used as an spi or gpio pin the int enable, int act low, 3.3v drive, high sink, open drain, and pull-up enable control the behavior of the pin the 50 ma sink drive capability is only available in the cy7c638xx. bit 7: spi use 0 = disable the spi alternate func tion. the pin is used as a gpio 1 = enable the spi function. the spi circ uitry controls the output of the pin important note for comm modes 01 or 10 (spi master or spi slave, see table 15-2 ): when configured for spi (spi use = 1 and comm modes [1:0] = spi master or spi slave mode), the input/output direction of pins p1.3, p1.5, and p1.6 is se t automatically by the spi logic. however, pin p1.4's input/output direction is not automaticall y set; it must be explicitly set by firmware. for spi master mode, pin p1.4 must be configured as an output; for spi slave mode, pin p1.4 must be configured as an input. table 14-15. p1.7 configuration (p17cr) [0x14] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 this register controls the ope ration of pin p1.7. this register only exists in cy7c638xx the 50 ma sink drive capability is only available in the cy7c638xx. the p1.7 gpio?s threshold is always set to ttl
cy7c63310 cy7c638xx document 38-08035 rev. *i page 36 of 74 15.0 serial peripheral interface (spi) the spi master/slave interface core logic runs on the spi cl ock domain, making its functionality independent of system clock speed. spi is a four pin serial interface comp rised of a clock, an enable and two data pins. 15.1 spi data register when an interrupt occurs to indicate to firmware that a byte of receive data is available, or the transmitter holding register is empty, firmware has 7 spi clocks to manage the buffers?to em pty the receiver buffer, or to refill the transmit holdi ng register. failu re to meet this timing requirement will result in incorrect data transfer. table 14-16. p2 configuration (p2cr) [0x15] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 this register only exists in cy7c638xx. this register controls the operation of pins p2.0?p2. 1. in the cy7c638xx, only 8 ma sink drive capability is available on this pin regardless of the setting of the high sink bit table 14-17. p3 configuration (p3cr) [0x16] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 0 this register exists in cy7c638xx. this regi ster controls the operat ion of pins p3.0?p3.1. in the cy7c638xx, only 8 ma sink drive capability is avail able on this pin regardless of the setting of the high sink bit table 15-1. spi data register (spidata) [0x3c] [r/w] bit # 7 6 5 4 3 2 1 0 field spidata[7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when read, this register returns the contents of the receive buffer. when written, it loads the transmit holding register bit [7:0]: spi data [7:0]
cy7c63310 cy7c638xx document 38-08035 rev. *i page 37 of 74 15.2 spi configure register table 15-2. spi configure re gister (spicr) [0x3d] [r/w] bit # 7 6 5 4 3 2 1 0 field swap lsb first comm mode cpol cpha sclk select read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: swap 0 = swap function disabled 1 = the spi block swaps its use of smosi and smiso. among othe r things, this can be useful in implementing single wire spi- like communications bit 6: lsb first 0 = the spi transmits and receives the msb (most significant bit) first 1 = the spi transmits and receives the lsb (least significant bit) first. bit [5:4]: comm mode [1:0] 0 0: all spi communication disabled 0 1: spi master mode 1 0: spi slave mode 1 1: reserved bit 3: cpol this bit controls the spi clock (sclk) idle polarity 0 = sclk idles low 1 = sclk idles high bit 2: cpha the clock phase bit controls the phase of the clock on which data is sampled. table 15-3 below shows the timing for the various combinations of lsb first, cpol, and cpha bit [1:0]: sclk select this field selects the speed of the master sclk. when in ma ster mode, sclk is generated by dividing the base cpuclk important note for comm modes 01b or 10b (spi master or spi slave): when configured for spi, (spi use = 1? table 14-14 ), the input/output direction of pins p1.3, p1.5, and p1.6 is set automati- cally by the spi logic. however, pin p1.4's input/output directio n is not automatically set; it must be explicitly set by firmw are. for spi master mode, pin p1.4 must be configured as an output ; for spi slave mode, pin p1.4 must be configured as an input.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 38 of 74 15.3 spi interface pins the spi interface uses the p1 .3?p1.6 pins. these pins are configured using the p1.3 an d p1.4?p1.6 configuration. table 15-3. spi mode timing vs. lsb first, cpol and cpha lsb first cpha cpol diagram 000 001 010 011 100 101 110 111 sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x x msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel x x data msb bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb sclk ssel data x msb x bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb
cy7c63310 cy7c638xx document 38-08035 rev. *i page 39 of 74 16.0 timer registers all timer functions of the encore ii are provided by a single timer block. the timer block is asynchronous from the cpu clock. 16.1 registers 16.1.1 free running counter the 16 bit free-running counter is clocked by the timer capture clo ck (tcapclk). it can be read in software for use as a genera l- purpose time base. when the low-order byte is read, the high-order byte is register ed. reading the high-order byte reads this register allowing the cpu to read the 16-bit value atomically (loads all bits at one time). the free-running timer generates an interrupt at 1024- s rate when clocked by a 4mhz source. it can also generate an interrupt when the free-running counter overflow occurs?every 16.384 ms(with a 4mhz source). this allo ws extending the length of the timer in software.. table 15-4. spi sclk frequency sclk select cpuclk divisor sclk frequency when cpuclk = 12 mhz 24 mhz 00 6 2 mhz 4 mhz 01 12 1 mhz 2 mhz 10 48 250 khz 500 khz 11 96 125 khz 250 khz figure 16-1. 16-bit free running counter block diagram timer capture clock 16-bit free running counter overflow interrupt/w rap interrupt 1024 s timer interrupt table 16-1. free-running timer low- order byte (frtmrl) [0x20] [r/w] bit # 7 6 5 4 3 2 1 0 field free-running timer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: free-running timer [7:0] this register holds the low-order byte of the 16-bit free-running timer. reading this register causes the high-order byte to be moved into a holding register allowing an automatic read of all 16 bits simultaneously. for reads, the actual read occurs in the cycle when the low order is read. for wr ites, the actual time th e write occurs is the cycle when the high order is written. when reading the free running timer, the low-order byte must be read first and the high-order second. when writing, the low- order byte must be written first then the high-order byte
cy7c63310 cy7c638xx document 38-08035 rev. *i page 40 of 74 table 16-2. free-running timer high- order byte (frtmrh) [0x21] [r/w] bit # 7 6 5 4 3 2 1 0 field free-running timer [15:8] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: free-running timer [15:8] when reading the free-running timer, the low-order byte must be read first and the high-order se cond. when writing, the low- order byte must be written first then the high-order byte table 16-3. timer capture 0 rising (tcap0r) [0x22] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 0 rising [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: capture 0 rising [7:0] this register holds the value of the free-running timer when the last rising edge occurred on the tcap0 input. when capture 0 is in 8-bit mode, the bits that are stored here are selected by the prescale [2:0] bi ts in the timer configuration register. wh en capture 0 is in 16-bit mode this register holds the lower order 8 bits of the 16-bit timer table 16-4. timer capture 1 rising (tcap1r) [0x23] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 1 rising [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: capture 1 rising [7:0] this register holds the value of the free-running timer when the last rising edge occurred on the tcap1 input. the bits that ar e stored here are selected by the prescale [2:0] bits in the timer configuration register. when capt ure 0 is in 16-bit mode this register holds the high-order 8 bits of the 16-bit timer from t he last capture 0 rising edge. when capture 0 is in 16-bit mode this register will be loaded with high-order 8 bits of the 16-bit timer on tcap0 rising edge table 16-5. timer capture 0 falling (tcap0f) [0x24] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 0 falling [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: capture 0 falling [7:0] this register holds the value of the free-running timer when the last falling edge occurred on the tcap0 input. when capture 0 is in 8-bit mode, the bits t hat are stored here are selected by the prescale [2:0] bits in the timer configuration register. when capture 0 is in 16-bit mode this register holds the lower-order 8 bits of the 16-bit timer table 16-6. timer capture 1 falling (tcap1f) [0x25] [r/w] bit # 7 6 5 4 3 2 1 0 field capture 1 falling [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: capture 1falling [7:0] this register holds the value of the free-running timer when t he last falling edge occurred on the tcap1 input. the bits that are stored here are selected by the prescale [2:0] bits in the timer configuration register. when capture 0 is in 16-bit mode t his register holds the high-order 8 bits of the 16-bit timer from th e last capture 0 falling edge. w hen capture 0 is in 16-bit mode this register will be loaded with high-order 8 bits of the 16-bit timer on tcap0 falling edge
cy7c63310 cy7c638xx document 38-08035 rev. *i page 41 of 74 16.1.2 timer capture encore ii has two 8-bit captures. each capture has separate registers for the rising and falling time. the two eight bit captures can be configured as a single 16-bit capture. when configured in this way, the capture 1 registers hold the high order byte of the 16-bit timer capture value. each of the four capture registers can be programmed to generatean interrupt when it is loaded. table 16-7. programmable interval timer low (pitmrl) [0x26] [r] bit # 7 6 5 4 3 2 1 0 field prog interval timer [7:0] read/write r r r r rr r r default 0 0 0 0 00 0 0 bit [7:0]: prog interval timer [7:0] this register holds the low-order byte of the 12-bit programmable interval timer. r eading this register c auses the high-order b yte to be moved into a holding register allowing an automatic read of all 12 bits simultaneously table 16-8. programmable interval timer high (pitmrh) [0x27] [r] bit # 7 6 5 4 3 2 1 0 field reserved prog interval timer [11:8] read/write ? ? ? ? rr r r default 0 0 0 0 00 0 0 bit [7:4]: reserved bit [3:0]: prog internal timer [11:8] this register holds the high-order nibble of the 12-bit progra mmable interval timer. reading th is register returns the high-ord er nibble of the 12-bit timer at the instan t that the low-order byte was last read table 16-9. programmable interval reload low (pirl) [0x28] [r/w] bit # 7 6 5 4 3 2 1 0 field prog interval [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:0]: prog interval [7:0] this register holds the lower 8 bits of the timer. while writi ng into the 12-bit reload register, write lower byte first then t he higher nibble table 16-10. programmable interval reload high (pirh) [0x29] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved prog interval[11:8] read/write ? ? ? ? r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:4]: reserved bit [3:0]: prog interval [11:8] this register holds the higher 4 bits of the timer. while writi ng into the 12-bit reload register, write lower byte first then the higher nibble
cy7c63310 cy7c638xx document 38-08035 rev. *i page 42 of 74 figure 16-2. programmable in terval timer block diagram system clock c lock tim er c onfiguration status and control 12-bit reload value 12-bit down counter 12-bit reload counter in te rru p t c ontroller table 16-11. timer configur ation (tmrcr) [0x2a] [r/w] bit # 7 6 5 4 3 2 1 0 field first edge hold 8-bit capture prescale [2:0] cap0 16bit enable reserved read/write r/w r/w r/w r/w r/w ? ? ? default 0 0 0 0 00 0 0 bit 7: first edge hold the first edge hold function applies to all four capture timers. 0 = the time of the most recent edge is held in the capture timer data register. if multiple edges have occurred since reading the capture timer, the time for the most recent one will be read 1 = the time of the first occurrence of an edge is held in t he capture timer data register un til the data is read. subsequent edges are ignored until the capture timer data register is read. bit [6:4]: 8-bit capture prescale [2:0] this field controls which 8 bits of the 16 free running timer are captured when in bit mode 0 0 0 = capture timer[7:0] 0 0 1 = capture timer[8:1] 0 1 0 = capture timer[9:2] 0 1 1 = capture timer[10:3] 1 0 0 = capture timer[11:4] 1 0 1 = capture timer[12:5] 1 1 0 = capture timer[13:6] 1 1 1 = capture timer[14:7] bit 3: cap0 16-bit enable 0 = capture 0 16-bit mode is disabled 1 = capture 0 16-bit mode is enabled. capture 1 is disabled and the capture 1 rising and falling registers are used as an exten sion to the capture 0 registers?extending them to 16 bits bit [2:0]: reserved
cy7c63310 cy7c638xx document 38-08035 rev. *i page 43 of 74 table 16-12. capture interrupt enable (tcapinte) [0x2b] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved cap1 fall enable cap1 rise enable cap0 fall enable cap0 rise enable read/write ???? r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:4]: reserved bit 3: cap1 fall enable 0 = disable the capture 1 falling edge interrupt 1 = enable the capture 1 falling edge interrupt bit 2: cap1 rise enable 0 = disable the capture 1 rising edge interrupt 1 = enable the capture 1 rising edge interrupt bit 1: cap0 fall enable 0 = disable the capture 0 falling edge interrupt 1 = enable the capture 0 falling edge interrupt bit 0: cap0 rise enable 0 = disable the capture 0 rising edge interrupt 1 = enable the capture 0 rising edge interrupt table 16-13. capture interrupt status (tcapints) [0x2c] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active read/write ???? r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit [7:4]: reserved bit 3: cap1 fall active 0 = no event 1 = a falling edge has occurred on cap1 bit 2: cap1 rise active 0 = no event 1 = a rising edge has occurred on cap1 bit 1: cap0 fall active 0 = no event 1 = a falling edge has occurred on cap0 bit 0: cap0 rise active 0 = no event 1 = a rising edge has occurred on cap0 note: the interrupt status bits must be cleared by firmware to enabl e subsequent interrupts. this is achieved by writing a ?1? to the corresponding interrupt status bit.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 44 of 74 figure 16-3. timer func tional timing diagram clk_captimer 16-bit free running counter clk_sys capture0 cap0_rise cap0_fall cap1_rise cap1_fall cap0_rise_reg cap0_fall_reg cap1_fall_reg cap1_rise_reg cap1_fall_reg cap1_rise_reg capture1 timing diagrams when cap0 is in 8 bit mode timing diagrams when cap0 is in 16 bit mode
cy7c63310 cy7c638xx document 38-08035 rev. *i page 45 of 74 figure 16-4. 16-bit free running counter loading timing diagram clk_sys write valid addr write data frt reload ready clk timer 12b prog timer 12b reload interrupt capture timer clk 16b free running counter load 16b free running counter 00a0 00a1 00a2 00a3 00a4 00a5 00a6 00a7 00a8 00a9 00ab 00ac 00ad 00ae 00af 00b0 00b1 00b2 acbe acbf acc0 16-bit free running counter loading timing 12-bit programmable timer load timing figure 16-5. memory mapped regi sters read/write timing diagram memory mapped registers read/write timing diagram clk_sys rd_wrn valid addr rdata wdata
cy7c63310 cy7c638xx document 38-08035 rev. *i page 46 of 74 17.0 interrupt controller the interrupt controller and it s associated registers allow the user?s code to respond to an interrupt from almost every functional block in the encore ii devices. the registers associated with the interrupt controller allow interrupts to be disabled either globally or individually. the registers also provide a mechanism by which a user may clear all pending and posted interrupts, or clear individual posted or pending interrupts. the following table lists all interrup ts and the priorities that are available in the encore ii devices. 17.1 architectural description an interrupt is posted when its interrupt conditions occur. this results in the flip-flop in figure 17-1 clocking in a ?1?. the interrupt will remain posted until the interrupt is taken or until it is cleared by writing to t he appropriate int_clrx register. a posted interrupt is not pending unless it is enabled by setting its interrupt mask bit (in the appropriate int_mskx register). all pending interrupts are processed by the priority encoder to determine the highest priority interrupt which will be taken by the m8c if the global interrupt enable bit is set in the cpu_f register. disabling an interrupt by clearing its interrupt mask bit (in the int_mskx register) does not clear a posted interrupt, nor does it prevent an interrupt from being posted. it simply prevents a posted interrupt from becoming pending. nested interrupts can be accomplished by re-enabling inter- rupts inside an interrupt service routine. to do this, set the ie bit in the flag register. a block diagram of the encore ii interrupt controller is shown in figure 17-1 . table 17-1. interrupt numb ers, priorities, vectors interrupt priority interrupt address name 0 0000h reset 1 0004h por/lvd 2 0008h int0 3 000ch spi transmitter empty 4 0010h spi receiver full 5 0014h gpio port 0 6 0018h gpio port 1 7 001ch int1 8 0020h ep0 9 0024h ep1 10 0028h ep2 11 002ch usb reset 12 0030h usb active 13 0034h 1 ms interval timer 14 0038h programmable interval timer 15 003ch timer capture 0 16 0040h timer capture 1 17 0044h 16-bit free running timer wrap 18 0048h int2 19 004ch ps2 data low 20 0050h gpio port 2 21 0054h gpio port 3 22 0058h reserved 23 005ch reserved 24 0060h reserved 25 0064h sleep timer table 17-1. interrupt numbers, priorities, vectors (contin- interrupt priority interrupt address name figure 17-1. interrupt co ntroller block diagram interrupt source (timer, gpio, etc.) interrupt tak en or posted interrupt pending interrupt gie interrupt vector mask bit setting d r q 1 priority encoder m8c c o r e interrupt request ... int_mskx int_clrx write cpu_f[0] ...
cy7c63310 cy7c638xx document 38-08035 rev. *i page 47 of 74 17.2 interrupt processing the sequence of events that o ccur during interrupt processing is as follows: 1. an interrupt becomes active, either because: a. the interrupt condition occurs (e.g., a timer expires) b. a previously posted interrupt is enabled through an up- date of an interrupt mask register c. an interrupt is pending and gie is set from 0 to 1 in the cpu flag register. 2. the current executing instruction finishes. 3. the internal interr upt is dispatched, taking 13 cycles. during this time, the following actions occur: he msb and lsb of program counter and flag registers (cpu_pc and cpu_f) are stored onto the pr ogram stack by an automatic call instruction (13 cycles) generated during the interrupt acknowledge process. a. the pch, pcl, and flag register (cpu_f) are stored onto the program stack (in that order) by an automatic call instruction (13 cycles) generated duri ng the inter- rupt acknowledge process b. the cpu_f register is then cleared. since this clears the gie bit to 0, additional interrupts are temporarily dis- abled c. the pch (pc[15:8]) is cleared to zero d. the interrupt vector is read from the interrupt controller and its value placed into pcl (pc[7:0]). this sets the program counter to point to the appropriate address in the interrupt table (e.g., 00 04h for the por/lvd inter- rupt) 4. program execution vectors to the interrupt table. typically, a ljmp instruction in the interrupt table sends execution to the user's interrupt service routine (isr) for this interrupt 5. the isr executes. note that interrupts are disabled since gie = 0. in the isr, interrupts can be re-enabled if desired by setting gie = 1 (care must be taken to avoid stack overflow). 6. the isr ends with a reti in struction which restores the program counter and flag registers (cpu_pc and cpu_f). the restored flag register re-enables interrupts, since gie = 1 again. 7. execution resumes at the next instruction, after the one that occurred before the interrupt. however, if there are more pending interrupts, the subsequent interrupts will be processed before the next normal program instruction. 17.3 interrupt trigger conditions trigger conditions for most interrupts in table 17-1. have been explained in the relevant sections. however, conditions under which the usb active (interrupt address 0030h) and ps2 data low (interrupt address 004ch) interrupts are triggered are explained below. 1. usb active interrupt: triggered when the d+/- lines are in a non-idle state i.e., k-state or se0 state 2. ps2 data low interrupt: triggered when sdata becomes low when the sdata pad is in the input mode for at least 6-7 32 khz cycles. 17.4 interrupt latency the time between the assertion of an enabled interrupt and the start of its isr can be calculated from the following equation. latency = time for current inst ruction to finish + time for internal interrupt routine to execute + time for ljmp instruction in interrupt table to execute. for example, if the 5-cycle jm p instruction is executing when an interrupt becomes active, the total number of cpu clock cycles before the isr begins would be as follows: (1 to 5 cycles for jmp to fi nish) + (13 cycles for interrupt routine) + (7 cycles for ljmp) = 21 to 25 cycles. in the example above, at 24 mh z, 25 clock cycles take 1.042 s. 17.5 interrupt registers the interrupt clear registers (int_clrx) are used to enable the individual interrupt sources? ability to clear posted inter- rupts. when an int_clrx register is read, any bits that are set indicates an interrupt has been posted for that hardware resource. therefore, reading these registers gives the user the ability to determine all posted interrupts. table 17-2. interrupt clear 0 (int_clr0) [0xda] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits will clear the posted interrupts for th e corresponding hardware. writing a ?1? to the bits and to the enswint (bit 7 of the int_msk3 register) will post the corresponding hardware interrupt table 17-3. interrupt clear 1 (int_clr1) [0xdb] [r/w] bit # 7 6 5 4 3 2 1 0 field tcap0 prog interval timer 1-ms timer usb active usb reset usb ep2 usb ep1 usb ep0 read/write r/w r/w r/w r/w r/w r/w r/w r/w
cy7c63310 cy7c638xx document 38-08035 rev. *i page 48 of 74 17.5.1 interrupt mask registers the interrupt mask registers (int_mskx) are used to enable the individual interrupt sources? ability to create pending inter- rupts. there are four interrupt mask registers (int_msk0, int_msk1, int_msk2, and int_msk3) which may be referred to in general as int_mskx. if cleared, each bit in an int_mskx register prevents a posted interrupt from becoming a pending interrupt (input to the priority encoder). however, an interrupt can still post even if its mask bit is zero. all int_mskx bits are independent of all other int_mskx bits. if an int_mskx bit is set, the interrupt source associated with that mask bit may generate an interrupt that will become a pending interrupt. the enable software interrupt (enswint) bit in int_msk3[7] determines the way an individual bit value written to an int_clrx register is interpreted. when is cleared, writing 1's to an int_clrx register has no effect. however, writing 0's to an int_clrx register, when enswint is cleared, will cause the corresponding interrupt to clea r. if the enswint bit is set, any 0s written to the int_clrx registers are ignored. however, 1s written to an int_clrx register, while enswint is set, will cause an interrupt to post for the corresponding interrupt. software interrupts can aid in debugging interrupt service routines by eliminat ing the need to crea te system level inter- actions that are sometimes necessary to create a hardware- only interrupt. default 00000000 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits will clear the posted interrupts for t he corresponding hardware. writing a 57?1? to the bits and to t he enswint (bit 7 of the int_msk3 register) will post the corresponding hardware interrupt table 17-4. interrupt clear 2 (int_clr2) [0xdc] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved reserved gpio port 3 gpio port 2 ps/2 data low int2 16-bit counter wrap tcap1 read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 when reading this register, 0 = there?s no posted interrupt for the corresponding hardware 1 = posted interrupt for the corresponding hardware present writing a ?0? to the bits will clear the posted interrupts for th e corresponding hardware. writing a ?1? to the bits and to the enswint (bit 7 of the int_msk3 register) will post the corresponding hardware interrupt table 17-3. interrupt clear 1 (int_clr1) [0xdb] [r/w] (continued) table 17-5. interrupt mask 3 (int_msk3) [0xde] [r/w] bit # 7 6 5 4 3 2 1 0 field enswint reserved read/write r/w ? ? ? ? ? ? ? default 0 0 0 0 00 0 0 bit 7: enable software interrupt (enswint) 0= disable. writing 0s to an int_clrx register, when enswin t is cleared, will cause the corresponding interrupt to clear 1= enable. writing 1s to an int_clrx register, when enswin t is set, will cause the corresponding interrupt to post. bit [6:0]: reserved table 17-6. interrupt mask 2 (int_msk2) [0xdf] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved reserved gpio port 3 int enable gpio port 2 int enable ps/2 data low int enable int2 int enable 16-bit counter wrap int enable tcap1 int enable read/write ? r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0
cy7c63310 cy7c638xx document 38-08035 rev. *i page 49 of 74 bit 7: reserved bit 6: gpio port 4 interrupt enable 0 = mask gpio port 4 interrupt 1 = unmask gpio port 4 interrupt bit 5: gpio port 3 interrupt enable 0 = mask gpio port 3 interrupt 1 = unmask gpio port 3 interrupt bit 4: gpio port 2 interrupt enable 0 = mask gpio port 2 interrupt 1 = unmask gpio port 2 interrupt bit 3: ps/2 data low interrupt enable 0 = mask ps/2 data low interrupt 1 = unmask ps/2 data low interrupt bit 2: int2 interrupt enable 0 = mask int2 interrupt 1 = unmask int2 interrupt bit 1: 16-bit counter wrap interrupt enable 0 = mask 16-bit counter wrap interrupt 1 = unmask 16-bit counter wrap interrupt bit 0: tcap1 interrupt enable 0 = mask tcap1 interrupt 1 = unmask tcap1 interrupt table 17-7. interrupt mask 1 (int_msk1) [0xe1] [r/w] bit # 7 6 5 4 3 2 1 0 field tcap0 int enable prog interval timer int enable 1-ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: tcap0 interrupt enable 0 = mask tcap0 interrupt 1 = unmask tcap0 interrupt bit 6: prog interval timer interrupt enable 0 = mask prog interval timer interrupt 1 = unmask prog interval timer interrupt bit 5: 1-ms timer interrupt enable 0 = mask 1-ms interrupt 1 = unmask 1-ms interrupt bit 4: usb active interrupt enable 0 = mask usb active interrupt 1 = unmask usb active interrupt bit 3: usb reset interrupt enable 0 = mask usb reset interrupt 1 = unmask usb reset interrupt bit 2: usb ep2 interrupt enable 0 = mask ep2 interrupt 1 = unmask ep2 interrupt bit 1: usb ep1 interrupt enable 0 = mask ep1 interrupt 1 = unmask ep1 interrupt bit 0: usb ep0 interrupt enable 0 = mask ep0 interrupt 1 = unmask ep0 interrupt table 17-6. interrupt mask 2 (int_msk2) [0xdf] [r/w] (continued) table 17-8. interrupt mask 0 (int_msk0) [0xe0] [r/w] bit # 7 6 5 4 3 2 1 0 field gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0
cy7c63310 cy7c638xx document 38-08035 rev. *i page 50 of 74 18.0 usb/ps2 transceiver although the usb transceiver has features to assist in interfacing to ps/2 these fe atures are not controlled using these regist ers. these registers only control the usb interf acing features. ps/2 interfacing options are controlled by the d+/d? gpio configu- ration register (see table 14-2 ). bit 7: gpio port 1 interrupt enable 0 = mask gpio port 1 interrupt 1 = unmask gpio port 1 interrupt bit 6: sleep timer interrupt enable 0 = mask sleep timer interrupt 1 = unmask sleep timer interrupt bit 5: int1 interrupt enable 0 = mask int1 interrupt 1 = unmask int1 interrupt bit 4: gpio port 0 interrupt enable 0 = mask gpio port 0 interrupt 1 = unmask gpio port 0 interrupt bit 3: spi receive interrupt enable 0 = mask spi receive interrupt 1 = unmask spi receive interrupt bit 2: spi transmit interrupt enable 0 = mask spi transmit interrupt 1 = unmask spi transmit interrupt bit 1: int0 interrupt enable 0 = mask int0 interrupt 1 = unmask int0 interrupt bit 0: por/lvd interrupt enable 0 = mask por/lvd interrupt 1 = unmask por/lvd interrupt table 17-8. interrupt mask 0 (int_msk0) [0xe0] [r/w] table 17-9. interrupt vector clea r register (int_vc) [0xe2] [r/w] bit # 7 6 5 4 3 2 1 0 field pending interrupt [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 the interrupt vector clear register (int_vc) holds the interrupt vector for the highest priority pending interrupt when read, a nd when written will clear all pending interrupts bit [7:0]: pending interrupt [7:0] 8-bit data value holds the interrupt vector for the highest prio rity pending interrupt. writing to this register will clear all pending interrupts.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 51 of 74 18.1 usb transceiver configuration table 18-1. usb transceiver configur e register (usbxcr) [0x74] [r/w] bit # 7 6 5 4 3 2 1 0 field usb pull-up enable reserved usb force state read/write r/w ? ? ? ? ? ? r/w default 0 0 0 0 00 0 0 bit 7: usb pull-up enable 0 = disable the pull-up resistor on d? 1 = enable the pull-up resistor on d?. this pull up is to v cc if vreg is not enabled or to the internally generated 3.3v when vreg is enabled bit [6:1]: reserved bit 0: usb force state this bit allows the state of the usb i/o pins d- and d+ to be forced to a state while usb is enabled 0 = disable usb force state 1 = enable usb force state. allows the d- and d+ pins to be controlled by p1.1 and p1.0 respectively when the usbio is in usb mode. refer to table 14-2 for more information note: the usb transceiver has a dedicated 3.3v regulator for usb signalling purposes and to prov ide for the 1.5k d-pull-up. unlike the other 3.3v regul ator, this regulator cannot be c ontrolled/accessed by firmware. when the device is suspended, this regulator is disabled along with the bandgap (which provides the reference voltage to the regulator) and the d-line is pulled u p to 5v through an alternate 6.5k resistor. during wake up follow ing a suspend, the band gap and the regulator are switched on in any order. under an extremely rare case when the device wakes up following a bus reset condition and the voltage regulator and the band gap turn on in that particular order, there is possibility of a glitch/l ow pulse occurring on the d- line. the hos t can misinterpret this as a deattach conditi on. this condition, although rare, can be avoided by keeping the bandgap circuitry enabled during sleep. this is achieved by setting the ?no buzz? bi t, bit[5] in the osc_cr0 register. this is an issue only if t he device is put to sleep during a bus reset condition.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 52 of 74 19.0 usb regulator output 19.1 vreg control 20.0 usb serial interface engine (sie) the sie allows the microcontroller to communicate with the usb host at low-speed data rates (1.5 mbps). the sie simplifies the interface between the microcontroller and usb by incorporating hardware that handles the following usb bus activity independently of the microcontroller: ? translate the encoded received data and format the data to be transmitted on the bus. ? crc checking and generation. flag the microcontroller if errors exist during transmission. ? address checking. ignore the transactions not addressed to the device. ? send appropriate ack/nak/stall handshakes. ? token type identification (setup, in, or out). set the appropriate token bit once a valid token is received. ? place valid received data in the appropriate endpoint fifos. ? send and update the data toggle bit (data1/0). ? bit stuffing/unstuffing. firmware is required to handle the rest of the usb interface with the following tasks: ? coordinate enumeration by decoding usb device requests. ? fill and empty the fifos. ? suspend/resume coordination. ? verify and select data toggle values. table 19-1. vreg control register (vregcr) [0x73] [r/w] bit # 7 6 5 4 3 2 1 0 field reserved keep alive vreg enable read/write ? ? ? ? ? ? r/w r/w default 0 0 0 0 00 0 0 bit [7:2]: reserved bit 1: keep alive keep alive, when set, allows the voltage regulator to source up to 20 a of current when the voltage regulator is disabled, p12cr[0],p12cr[7] must be cleared. 0 = disabled 1 = enabled bit 0: vreg enable this bit turns on the 3.3v voltage regulator. the voltage regulator only functions within specifications when v cc is above 4.35v. this block must not be enabled when v cc is below 4.35v?although no damage or irregula rities will occur if it is enabled below 4.35v 0 = disable the 3.3v voltage regulator output on the vreg/p1.2 pin 1 = enable the 3.3v voltage regulator output on the vreg/p1.2 pin. gpio functi onality of p1.2 is disabled note: use of the alternate drive on pins p1.3 ?p1.6 requires that the vreg enable bit be set to enable the regulator and pro- vide the alternate voltage
cy7c63310 cy7c638xx document 38-08035 rev. *i page 53 of 74 21.0 usb device 21.1 usb device address 21.2 endpoint 0, 1, and 2 count table 21-1. usb device ad dress (usbcr) [0x40] [r/w] bit # 7 6 5 4 3 2 1 0 field usb enable device address[6:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 the content of this register is cleared when a usb bus reset condition occurs bit 7: usb enable this bit must be enabled by firmware before the serial interface engine (sie) will respond to usb traffic at the address specif ied in device address [6:0]. when this bit is cleared, the usb tran sceiver enters power-down state. user?s firmware must clear this bit prior to entering sleep mode to save power 0 = disable usb device address and put the usb transceiver into power-down state 1 = enable usb device address and put the u sb transceiver into normal operating mode bit [6:0]: device address [6:0] these bits must be set by firmware during the usb enumeration process (i.e., setaddress) to the non-zero address assigned by the usb host table 21-2. endpoint 0, 1, and 2 coun t (ep0cnt?ep2cnt) [0x41, 0x43, 0x45] [r/w] bit # 7 6 5 4 3 2 1 0 field data toggle data valid reserved byte count[3:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: data toggle this bit selects the data packet's toggle state. for in transa ctions, firmware must set this bit to the select the transmitted data toggle. for out or setup transactions, the hardware sets th is bit to the state of the received data toggle bit. 0 = data0 1 = data1 bit 6: data valid this bit is used for out and setup tokens only. this bit is clea red to ?0? if crc, bitstuff, or pid errors have occurred. this bit does not update for some endpoint mode settings 0 = data is invalid. if enabled, the endpoint interrupt will occur even if invalid data is received 1 = data is valid bit [5:4]: reserved bit [3:0]: byte count bit [3:0] byte count bits indicate the number of data bytes in a transact ion: for in transactions, firmwar e loads the count with the numb er of bytes to be transmitted to the host from the endpoint fifo. valid values are 0 to 8 inclusive. for out or setup transactions , the count is updated by hardware to the number of data bytes received, plus 2 for the crc bytes. valid values are 2?10 inclusiv e. for endpoint 0 count register, whenever the count updates from a setup or ou t transaction, the c ount register locks and cannot be written by the cpu. r eading the register unlocks it. th is prevents firmware from overwr iting a status update on it.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 54 of 74 21.3 endpoint 0 mode because both firmware and the sie are allowed to write to the endpoint 0 mode and count r egisters the sie provides an interlocking mechanism to prevent accidental overwriting of data. when the sie writes to these r egisters they are locked and the processor cannot write to them until after it has read them. writing to this register clears the upper four bits regardless of the value written. table 21-3. endpoint 0 mode (ep0mode) [0x44] [r/w] bit # 7 6 5 4 3 2 1 0 field setup received in received out received ack?d trans mode[3:0] read/write r/c[4] r/c [4] r/c [4] r/c [4] r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: setup received this bit is set by hardware when a valid setup packet is receiv ed. it is forced high from the start of the data packet phase of the setup transactions until the end of the data phase of a c ontrol write transfer and cannot be cleared during this interval. while this bit is set to ?1?, the cpu cannot write to the ep0 fifo. this prevents firmware fr om overwriting an incoming setup transaction before firmware has a chance to read the setup data. this bit is cleared by any non-locked writes to the register. 0 = no setup received 1 = setup received bit 6: in received this bit when set indicates a valid in packet has been received. this bit is updated to ?1? after the host acknowledges an in d ata packet.when clear, it indicates either no in has been received or that the host didn?t acknowle dge the in data by sending ack handshake. this bit is cleared by any non-locked writes to the register. 0 = no in received 1 = in received bit 5: out received this bit when set indicates a valid out packet has been received and acked. this bit is updated to ?1? after the last received packet in an out transaction. when clear, it indicates no out received. this bit is cleared by any non-locked writes to the register. 0 = no out received 1 = out received bit 4: ack?d transaction the ack?d transaction bit is set whenever the sie engages in a tr ansaction to the register?s endpoint that completes with a ack packet. this bit is cleared by any non-locked writes to the register 1 = the transaction completes with an ack 0 = the transaction does not complete with an ack bit [3:0]: mode [3:0] the endpoint modes determine how the sie responds to usb traf fic that the host sends to the endpoint. the mode controls how the usb sie responds to traffic and how the usb sie will change the mode of that endpoint as a result of host packets to the endpoint.
cy7c63310 cy7c638xx document 38-08035 rev. *i page 55 of 74 21.4 endpoint 1 and 2 mode table 21-4. endpoint 1 and 2 mode (ep1mode ? ep2mode) [0x45, 0x46] [r/w] bit # 7 6 5 4 3 2 1 0 field stall reserved nak int enable ack?d transaction mode[3:0] read/write r/w r/w r/w r/c (note 4) r/w r/w r/w r/w default 0 0 0 0 00 0 0 bit 7: stall when this bit is set the sie will stall an out packet if the mode bits are set to ack-out, and the sie will stall an in packet if the mode bits are set to ack-in. this bit must be clear for all other modes bit 6: reserved bit 5: nak int enable this bit when set causes an endpoint interr upt to be generated even when a transfer completes with a nak. unlike encore, encore ii family members do not generate an endpoint inte rrupt under these conditions unless this bit is set 0 = disable interrupt on nak?d transactions 1 = enable interrupt on nak?d transaction bit 4: ack?d transaction the ack?d transaction bit is set whenever the sie engages in a transaction to the register?s endpoint that completes with an ack packet. this bit is cleared by any writes to the register 0 = the transaction does not complete with an ack 1 = the transaction completes with an ack bit [3:0]: mode [3:0] the endpoint modes determine how the sie responds to usb traffic that the host sends to the endpoint. the mode controls how the usb sie responds to traffic and how the usb sie will change the mode of that endpoint as a result of host packets to the endpoi nt. note: when the sie writes to the ep1mode or the ep2mode register it blocks firmware writes to the ep2mode or the ep1mode registers respectively (if both writes occur in the same clock cycle). this is because the design employs only one common ?upda te? signal for both ep1mode and ep2mode regist ers. thus, when sie writes to say ep1mo de register, the update signal is set and this prevents firmware writes to ep2mode register. sie writes to the endpoint mode registers have higher priority than firmware writes. this mode register write block si tuation can put the endpoints in incorrect modes. firmware must read the ep1/2mode reg is- ters immediately following a firmware write and rewrite if the value read is incorrect. table 21-5. endpoint 0 data (ep0data) [0x50-0x57] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 0 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 0 buffer is comprised of 8 bytes located at address 0x50 to 0x57 table 21-6. endpoint 1 data (ep1data) [0x58-0x5f] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 1 data buffer [7:0] read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 1buffer is comprised of 8 bytes located at address 0x58 to 0x5f table 21-7. endpoint 2 data (ep2data) [0x60-0x67] [r/w] bit # 7 6 5 4 3 2 1 0 field endpoint 2 data buffer [7:0]
cy7c63310 cy7c638xx document 38-08035 rev. *i page 56 of 74 the three data buffers used to hold data for both in and out transactions. each data buffer is 8 bytes long. the reset values of the endpoint data registers are unknown. unlike past encore parts the usb data buffers are only accessible in the i/o space of the processor. 22.0 usb mode tables mode column the 'mode' column contains the mnemonic names given to the modes of the endpoint. the mo de of the endpoint is deter- mined by the four-bit binaries in the 'encoding' column as discussed below. the status in and status out represent the status in or out stage of the control transfer. encoding column the contents of the 'encoding' column represent the mode bits [3:0] of the endpoint mode registers ( table 21-3 and table 21-4 ). the endpoint modes determine how the sie responds to different tokens that the host sends to the endpoints. for example, if the mode bits [3:0] of the endpoint 0 mode register are set to '0001', which is nak in/out mode, the sie will send an ack handshake in response to setup tokens and nak any in or out tokens. setup, in, and out columns depending on the mode specified in the 'encoding' column, the 'setup', 'in', and 'out' columns contain the sie's responses when the endpoint receives setup, in, and out tokens, respectively. a 'check' in the out column means that upon receiving an out token the sie checks to se e whether the out is of zero length and has a data toggle (dat a1/0) of 1. if these condi- tions are true, the sie responds with an ack. if any of the above conditions is not met, th e sie will respond with either a stall or ignore. read/write r/w r/w r/w r/w r/w r/w r/w r/w default unknown unknown unknown unknown unknown unknown unknown unknown the endpoint 2 buffer is comprised of 8 bytes located at address 0x60 to 0x67 table 21-7. endpoint 2 data (ep2data) [0x60-0x67] [r/w] (continued) mode encoding setup in out comments disable 0000 ignore ignore ignore ignore all usb traffic to this endpoint. used by data and control endpoints nak in/out 0001 accept nak nak nak in and out token. control endpoint only status out only 0010 accept stall check stall in and ack zero byte out. control endpoint only stall in/out 0011 accept stall stall stall in and out token. control endpoint only status in only 0110 accept tx0 byte stall stall out and send zero byte data for in token. con- trol endpoint only ack out ? status in 1011 accept tx0 byte ack ack the out token or send zero byte data for in token. control endpoint only ack in ? status out 1111 accept tx count check respond to in data or status out. control endpoint only nak out 1000 ignore ignore nak send nak handshake to out token. data endpoint only ack out (stall = 0) 1001 ignore ignore ack this mode is changed by the sie to mode 1000 on is- suance of ack handshake to an out. data endpoint only ack out (stall = 1) 1001 ignore ignore stall stall the out transfer nak in 1100 ignore nak ignore send nak handshake for in token. data endpoint only ack in (stall = 0) 1101 ignore tx count ignore this mode is changed by the sie to mode 1100 after receiving ack handshake to an in data. data endpoint only ack in (stall = 1) 1101 ignore stall ignore stall the in transfer. data endpoint only reserved 0101 ignore ignore ignore these modes are not supported by sie. firmware must not use this mode in control and data endpoints reserved 0111 ignore ignore ignore reserved 1010 ignore ignore ignore reserved 0100 ignore ignore ignore reserved 1110 ignore ignore ignore
cy7c63310 cy7c638xx document 38-08035 rev. *i page 57 of 74 a 'tx count' entry in the in column means that the sie will transmit the number of bytes s pecified in the byte count bit [3:0] of the endpoint count register ( table 21-2 ) in response to any in token. 23.0 details of mode for differing traffic conditions control endpoint sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo disabled 0000 x x x x ignore all stall_in_out 0011 setup >10 x x junk ignore 0011 setup <=10 invalid x junk ignore 0011 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0011 in x x x stall stall in 0011 out >10 x x ignore 0011 out <=10 invalid x ignore 0011 out <=10 valid x stall stall out nak_in_out 0001 setup >10 x x junk ignore 0001 setup <=10 invalid x junk ignore 0001 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0001 in x x x nak nak in 0001 out >10 x x ignore 0001 out <=10 invalid x ignore 0001 out <=10 valid x nak nak out ack_in_status_out 1111 setup >10 x x junk ignore 1111 setup <=10 invalid x junk ignore 1111 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 1111 in x x x tx host not ack'd 1111 in x x x tx 1 1 0001 yes host ack'd 1111 out >10 x x ignore 1111 out <=10 invalid x ignore 1111 out <=10, <>2 valid x stall 0011 yes bad status 1111 out 2 valid 0 stall 0011 yes bad status 1111 out 2 valid 1 ack 1 1 0010 1 1 2 yes good status status_out 0010 setup >10 x x junk ignore 0010 setup <=10 invalid x junk ignore 0010 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0010 in x x x stall 0011 yes stall in 0010 out >10 x x ignore 0010 out <=10 invalid x ignore 0010 out <=10, <>2 valid x stall 0011 yes bad status 0010 out 2 valid 0 stall 0011 yes bad status 0010 out 2 valid 1 ack 1 1 1 1 2 yes good status ack_out_status_in 1011 setup >10 x x junk ignore 1011 setup <=10 invalid x junk ignore 1011 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup
cy7c63310 cy7c638xx document 38-08035 rev. *i page 58 of 74 1011 in x x x tx 0 host not ack'd 1011 in x x x tx 0 1 1 0011 yes host ack'd 1011 out >10 x x junk ignore 1011 out <=10 invalid x junk ignore 1011 out <=10 valid x ack 1 1 0001 update 1 update data yes good out status_in 0110 setup >10 x x junk ignore 0110 setup <=10 invalid x junk ignore 0110 setup <=10 valid x ack 1 1 0001 update 1 update data yes ack setup 0110 in x x x tx 0 host not ack'd 0110 in x x x tx 0 1 1 0011 yes host ack'd 0110 out >10 x x ignore 0110 out <=10 invalid x ignore 0110 out <=10 valid x stall 0011 yes stall out data out endpoints sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo ack out (stall bit = 0) 1001 in x x x ignore 1001 out >max x x junk ignore 1001 out <=max invalid invalid junk ignore 1001 out <=max valid valid ack 1 1000 update 1 update data yes ack out ack out (stall bit = 1) 1001 in x x x ignore 1001 out >max x x ignore 1001 out <=max invalid invalid ignore 1001 out <=max valid valid stall stall out nak out 1000 in x x x ignore 1000 out >max x x ignore 1000 out <=max invalid invalid ignore 1000 out <=max valid valid nak if enabled nak out data in endpoints sie bus event sie ep0 mode register ep0 count register ep0 interrupt comments mode token count dval d0/1 response s i o a mode dtog dval count fifo ack in (stall bit = 0) 1101 out x x x ignore 1101 in x x x host not ack'd 1101 in x x x tx 1 1100 yes host ack'd ack in (stall bit = 1) 1101 out x x x ignore 1101 in x x x stall stall in nak in 1100 out x x x ignore 1100 in x x x nak if enabled nak in 23.0 details of mode for differing traffic conditions (continued)
cy7c63310 cy7c638xx document 38-08035 rev. *i page 59 of 74 24.0 register summary addr name 7 6 5 4 3 2 1 0 r/w default 00 p0data p0.7 p0.6/tio1 p0.5/tio0 p0.4/int2 p0.3/int1 p0.2/int0 p0.1/clk- out p0.0/clki n bbbbbbbb 00000000 01 p1data p1.7 p1.6/smi so p1.5/smo si p1.4/sclk p1.3/ssel p1.2/vreg p1.1/d? p1.0/d+ bbbbbbbb 00000000 02 p2data res p2.1?p2.0 bbbbbbbb 00000000 03 p3data res p3.1?p3.0 bbbbbbbb 00000000 04 p4data res res ----bbbb 00000000 05 p00cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 06 p01cr clk output int enable int act low ttl thresh reserved open drain pull-up enable output enable bbbbbbbb 00000000 07?09 p02cr? p04cr reserved reserved int act low ttl thresh reserved open drain pull-up enable output enable --bbbbbb 00000000 0a?0b p05cr? p06cr tio output int enable int act low ttl thresh reserved open drain pull-up enable output enable bbbbbbbb 00000000 0c p07cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 0d p10cr reserved int enable int act low reserved ps/2 pull- up enable output enable -bb---bb 00000000 0e p11cr reserved int enable int act low reserved open drain reserved output enable -bb--b-b 00000000 0f p12cr clk output int enable int act low ttl thresh reserved open drain pull-up enable output enable bbbbbbbb 00000000 10 p13cr reserved int enable int act low 3.3v drive high sink open drain pull-up enable output enable -bbbbbbb 00000000 11?13 p14cr? p16cr spi use int enable int act low 3.3v drive high sink open drain pull-up enable output enable bbbbbbbb 00000000 14 p17cr reserved int enable int act low ttl thresh high sink open drain pull-up enable output enable -bbbbbbb 00000000 15 p2cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 16 p3cr reserved int enable int act low ttl thresh reserved open drain pull-up enable output enable -bbbbbbb 00000000 20 frtmrl free running timer [7:0] bbbbbbbb 00000000 21 frtmrh free running timer [15:8] bbbbbbbb 00000000 22 tcap0r capture 0 rising [7:0] bbbbbbbb 00000000 23 tcap1r capture 1 rising [7:0] bbbbbbbb 00000000 24 tcap0f capture 0 falling [7:0] bbbbbbbb 00000000 25 tcap1f capture 1 falling [7:0] bbbbbbbb 00000000 26 pitmrl prog interval timer [7:0] bbbbbbbb 00000000 27 pitmrh reserved prog interval timer [11:8] ----bbbb 00000000 28 pirl prog interval [7:0] bbbbbbbb 00000000 29 pirh reserved prog interval [11:8] ----bbbb 00000000 2a tmrcr first edge hold 8-bit capture prescale cap0 16bit enable reserved bbbbb--- 00000000 2b tcapinte reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active ----bbbb 00000000 2c tcapints reserved cap1 fall active cap1 rise active cap0 fall active cap0 rise active ----bbbb 00000000 30 cpuclkcr reserved usb clk/2 disable usb clk select reserved cpu clk select -bb----b 00010000 31 itmrclkcr tcapclk divider tcapclk select itmrclk divider itmrclk select bbbbbbbb 1000 1111 32 clkiocr reserved reserved clkout select ---bbbbb 00000000 34 iosctr foffset[2:0] gain[4:0] bbbbbbbb 000ddddd 36 lposctr 32-khz low power reserved 32-khz bias trim [1:0] 32-khz freq trim [3:0] b-bbbbbb dddddddd 39 osclckcr reserved fine tune only usb osclock disable ------bb 00000000
cy7c63310 cy7c638xx document 38-08035 rev. *i page 60 of 74 legend in the r/w column, b = both read and write r = read only w = write only c = read/clear ? = unknown d = calibration value. must not change during normal use. 3c spidata spidata[7:0] bbbbbbbb 00000000 3d spicr swap lsb first comm mode cpol cpha sclk select bbbbbbbb 00000000 40 usbcr usb enable device address[6:0] bbbbbbbb 00000000 41 ep0cnt data to g g l e data valid reserved byte count[3:0] bbbbbbbb 00000000 42 ep1cnt data to g g l e data valid reserved byte count[3:0] bbbbbbbb 00000000 43 ep2cnt data to g g l e data valid reserved byte count[3:0] bbbbbbbb 00000000 44 ep0mode setup rcv?d in rcv?d out rcv?d ack?d trans mode[3:0] ccccbbbb 00000000 45 ep1mode stall reserved nak int enable ack?d trans mode[3:0] b-bcbbbb 00000000 46 ep2mode stall reserved nak int enable ack?d trans mode[3:0] b-bcbbbb 00000000 50?57 ep0data endpoint 0 data buffer [7:0] bbbbb bbb ???????? 58?5f ep1data endpoin t 1 data buffer [7:0] bbbbb bbb ???????? 60?67 ep2data endpoint 2 data buffer [7:0] bbbbb bbb ???????? 73 vregcr reserved keep alive vreg enable ------bb 00000000 74 usbxcr usb pull- up enable reserved usb force state b------b 00000000 da int_clr0 gpio port 1 sleep timer int1 gpio port 0 spi receive spi transmit int0 por/lvd bbbbbbbb 00000000 db int_clr1 tcap0 prog interval timer 1-ms timer usb active usb reset usb ep2 usb ep1 usb ep0 bbbbbbbb 00000000 dc int_clr2 reserved reserved gpio port 3 gpio port 2 ps/2 data low int2 16-bit counter wrap tcap1 -bbbbbbb 00000000 de int_msk3 enswint reserved b------- 00000000 df int_msk2 reserved reserved gpio port 3 int enable gpio port 2 int enable ps/2 data low int enable int2 int enable 16-bit counter wrap int enable tcap1 int enable -bbbbbbb 00000000 e1 int_msk1 tcap0 int enable prog interval timer int enable 1-ms timer int enable usb active int enable usb reset int enable usb ep2 int enable usb ep1 int enable usb ep0 int enable bbbbbbbb 00000000 e0 int_msk0 gpio port 1 int enable sleep timer int enable int1 int enable gpio port 0 int enable spi receive int enable spi transmit int enable int0 int enable por/lvd int enable bbbbbbbb 00000000 e2 int_vc pending interrupt [7:0] bbbbbbbb 00000000 e3 reswdt reset watchdog timer [7:0] wwwwwwww 00000000 -- cpu_a temporary register t1 [7:0] -------- 00000000 -- cpu_x x[7:0] -------- 00000000 -- cpu_pcl program counter [7:0] -------- 00000000 -- cpu_pch program counter [15:8] -------- 00000000 -- cpu_sp stack pointer [7:0] -------- 00000000 - cpu_f reserved xoi super carry zero global ie ---brwww 00000010 ff cpu_scr gies reserved wdrs pors sleep reserved reserved stop r-ccb--b 00010000 1e0 osc_cr0 reserved no buzz sleep timer [1:0] cpu speed [2:0] --bbbbbb 00000000 1e3 lvdcr reserved porlev[1:0] reserved vm[2:0] --bb-bbbb 00000000 1eb eco_tr sleep duty cycle [1:0] reserved bb------ 00000000 1e4 vltcmp reserved lvd ppor ------rr 00000000 24.0 register summary (continued) addr name 7 6 5 4 3 2 1 0 r/w default
cy7c63310 cy7c638xx document 38-08035 rev. *i page 61 of 74 25.0 absolute maximum ratings storage temperature ..................................?65c to +150c ambient temperature with power applied ..... ?0c to +70c supply voltage on v cc relative to v ss .......... ?0.5v to +7.0v dc input voltage ................................ ?0.5v to + v cc + 0.5v dc voltage applied to outputs in high-z state ...................................... ?0.5v to + v cc + 0.5v maximum total sink output current into port 0 and 1 and pins............................................................. 70 ma maximum total source output current into gpio pins30 ma maximum on-chip power dissipation on any gpio pin......................................................... 50 mw power dissipation . .............. .............. .............. ......... 300 mw static discharge voltage ............................................. 2200v latch-up current ...................................................... 200 ma 26.0 dc characteristics parameter description conditions min. typical max. unit general v cc1 operating voltage no usb activity, cpu speed < 12 mhz 4.0 5.5 v v cc2 operating voltage usb activity, cpu speed < 12 mhz 4.35 5.25 v v cc3 operating voltage flash programming 4.35 5.25 v v cc4 operating voltage no usb activity, cpu speed < 24 mhz 4.75 5.5 v t fp operating temp flash programming 0 70 c i cc1 v cc operating supply current v cc = 5.25v, no gpio loading, 24 mhz 40 ma i cc2 v cc operating supply current v cc = 5.0v, no gpio loading, 6 mhz 10 ma i sb1 standby current internal and external oscillators, bandgap, flash, cpu clock, timer clock, usb clock all disabled 10 a low-voltage detect v lvd low-voltage detect trip voltage (8 programmable trip points) 2.681 4.872 v 3.3v regulator i vreg max regulator output current 4.35v < v cc < 5.5v 125 ma i ka keep alive current when regulator is disabled with ?keep alive? enable 20 a v ka keep alive voltage keep alive bit set in vregcr 2.35 3.8 v v reg1 v reg output voltage v cc > 4.35v, 0 < temp < 40c, 25 ma < i vreg < 125 ma (3.3v 8%) t = 0 to 70c 3.0 3.6 v v reg2 v reg output voltage v cc > 4.35v, 0 < temp < 40c, 1 ma < i vreg < 25 ma (3.3v 4%) t = 0 to 40c 3.15 3.45 v c load capacitive load on vreg pin 1 2 f ln reg line regulation 1%/v ld reg load regulation 0.04 %/ma usb interface v on static output high 15k 5% ohm to v ss 2.8 3.6 v v off static output low r up is enabled 0.3 v v di differential input sensitivity 0.2 v v cm differential input common mode range 0.8 2.5 v v se single ended receiver threshold 0.8 2 v c in transceiver capacitance 20 pf i io hi-z state data line leakage 0v < v in < 3.3v ?10 10 a
cy7c63310 cy7c638xx document 38-08035 rev. *i page 62 of 74 ps/2 interface v olp static output low sdata or sclk pins 0.4 v r ps2 internal ps/2 pull up resistance sdat a, sclk pins, ps/2 enabled 3 7 k ? general purpose i/o interface r up pull up resistance 4 12 k ? v icr input threshold voltage low, cmos mode low to high edge 40% 65% v cc v icf input threshold voltage low, cmos mode high to low edge 30% 55% v cc v hc input hysteresis voltage, cmos mode high to low edge 3% 10% v cc v ilttl input low voltage, ttl mode i/o-pin supply = 2.9?3.6v 0.8 v v ihttl input high voltage, ttl mode i/o-pin supply = 4.0?5.5v 2.0 v v ol1 output low voltage, high drive [5] i ol1 = 50 ma 0.8 v v ol2 output low voltage, high drive [5] i ol1 = 25 ma 0.4 v v ol3 output low voltage, low drive [6] i ol2 = 8 ma 0.4 v v oh output high voltage [6] i oh = 2 ma v cc ? 0.5 v c load maximum load capacitance 50 pf 27.0 ac characteristics parameter description conditions min. typical max. unit clock t eclkdc external clock duty cycle 45 55 % t eclk1 t eclk2 external clock frequency external clock frequency external clock is the source of the cpuclk external clock is not the source of the cpuclk 0.187 0 24 24 mhz mhz 3.3v regulator v orip output ripple voltage 10hz to 100mhz at cload = 1 f200mv p-p usb driver t r1 transition rise time c load = 200 pf 75 ns t r2 transition rise time c load = 600 pf 300 ns t f1 transition fall time c load = 200 pf 75 ns t f2 transition fall time c load = 600 pf 300 ns t r rise/fall time matching 80 125 % v crs output signal crossover voltage 1.3 2.0 v usb data timing t drate low-speed data rate ave. bit rate (1.5 mbps 1.5%) 1.4775 1.5225 mbps t djr1 receiver data jitter tolerance to next transition ?75 75 ns t djr2 receiver data jitter tolerance to pair transition ?45 45 ns t deop differential to eop transition skew ?40 100 ns 26.0 dc characteristics (continued) parameter description conditions min. typical max. unit general
cy7c63310 cy7c638xx document 38-08035 rev. *i page 63 of 74 1 t eopr1 eop width at receiver rejects as eop 330 ns t eopr2 eop width at receiver accept as eop 675 ns t eopt source eop width 1.25 1.5 s t udj1 differential driver jitter to next transition ?95 95 ns t udj2 differential driver jitter to pair transition ?95 95 ns t lst width of se0 during diff. transition 210 ns non-usb mode driver characteristics t fps2 sdata/sck transition fall time 50 300 ns gpio timing t r_gpio output rise time measured between 10 and 90% vdd/vreg with 50 pf load 50 ns t f_gpio output fall time measured between 10 and 90% vdd/vreg with 50 pf load 15 ns spi timing t smck spi master clock rate f cpuclk /6 2 mhz t ssck spi slave clock rate 2.2 mhz t sckh spi clock high time high for cpol = 0, low for cpol = 1 125 ns t sckl spi clock low time low for cpol = 0, high for cpol = 1 125 ns t mdo master data output time [5] sck to data valid ?25 50 ns t mdo1 master data output time, first bit with cpha = 0 time before leading sck edge 100 ns t msu master input data set-up time 50 ns t mhd master input data hold time 50 ns t ssu slave input data set-up time 50 ns t shd slave input data hold time 50 ns t sdo slave data output time sck to data valid 100 ns t sdo1 slave data output time, first bit with cpha = 0 time after ss low to data valid 100 ns t sss slave select set-up time be fore first sck edge 150 ns t ssh slave select hold time after last sck edge 150 ns 27.0 ac characteristics (continued) parameter description conditions min. typical max. unit note 5. in master mode first bit is available 0.5 spiclk cycle before master clock edge available on the sclk pin. figure 27-1. clock timing clock t cyc t cl t ch
cy7c63310 cy7c638xx document 38-08035 rev. *i page 64 of 74 figure 27-2. gpio timing diagram figure 27-3. usb data signal timing 10% t r_gpio t f_gpio gpio pin output voltage 90% 90% 10% 90% 10% d ? d + t r t f v crs v oh v ol figure 27-4. receiver jitter tolerance differential data lines paired transitions n * t period + t jr2 t period consecutive transitions n * t period + t jr1 t jr t jr1 t jr2
cy7c63310 cy7c638xx document 38-08035 rev. *i page 65 of 74 figure 27-5. different ial to eop transition skew and eop width t period differential data lines crossover point crossover point extended source eop width: t eopt receiver eop width: t eopr1 , t eopr2 diff. data to se0 skew n * t period + t deop figure 27-6. differe ntial data jitter t period differential data lines crossover points paired transitions n * t period + t xjr2 consecutive transitions n * t period + t xjr1
cy7c63310 cy7c638xx document 38-08035 rev. *i page 66 of 74 figure 27-7. spi master timing, cpha = 1 msb t msu lsb t mhd t sckh t mdo ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl msb lsb figure 27-8. spi slave timing, cpha = 1 msb t ssu lsb t shd t sckh t sdo ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sss t ssh msb lsb
cy7c63310 cy7c638xx document 38-08035 rev. *i page 67 of 74 figure 27-9. spi master timing, cpha = 0 figure 27-10. spi slave timing, cpha = 0 msb t msu lsb t mhd t sckh t mdo1 ss sck (cpol=0) sck (cpol=1) mosi miso (ss is under firmware control in spi master mode) t sckl t mdo lsb msb msb t ssu lsb t shd t sckh t sdo1 ss sck (cpol=0) sck (cpol=1) mosi miso t sckl t sdo lsb msb t sss t ssh 28.0 ordering information ordering code flash size ram size package type cy7c63833-lfxc 8k 256 32-qfn cy7c63823-sxc 8k 256 24-soic cy7c63823-qxc 8k 256 24-qsop
cy7c63310 cy7c638xx document 38-08035 rev. *i page 68 of 74 cy7c63813-pxc 8k 256 18-pdip cy7c63813-sxc 8k 256 18-soic CY7C63803-sxc 8k 256 16-soic cy7c63801-pxc 4k 256 16-pdip cy7c63801-sxc 4k 256 16-soic cy7c63310-pxc 3k 128 16-pdip cy7c63310-sxc 3k 128 16-soic 29.0 package diagrams figure 29-1. 16-lead(300-mil) molded dip p1 28.0 ordering information (continued) ordering code flash size ram size package type 51-85009-*a
cy7c63310 cy7c638xx document 38-08035 rev. *i page 69 of 74 figure 29-2. 16-lead (150-mil) soic s16.15 figure 29-3. 18-lead(300-mil) molded dip p3 29.0 package diagrams (continued) pin 1 id 0~8 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms 51-85068-*b 51-85010-*b
cy7c63310 cy7c638xx document 38-08035 rev. *i page 70 of 74 figure 29-4. 18-lead(300-mil) molded soic s3 29.0 package diagrams (continued) pin 1 id seating plane 0.447[11.353] 0.463[11.760] 18 lead (300 mil) soic - s3 1 9 10 18 * * * dimensions in inches[mm] min. max. 0.291[7.391] 0.300[7.620] 0.394[10.007] 0.419[10.642] 0.050[1.270] typ. 0.092[2.336] 0.105[2.667] 0.004[0.101] 0.0118[0.299] 0.0091[0.231] 0.0125[0.317] 0.015[0.381] 0.050[1.270] 0.013[0.330] 0.019[0.482] 0.026[0.660] 0.032[0.812] 0.004[0.101] reference jedec mo-119 part # s18.3 standard pkg. sz18.3 lead free pkg. 51-85023-*b
cy7c63310 cy7c638xx document 38-08035 rev. *i page 71 of 74 figure 29-5. 24-lead (300-mil) soic s13 figure 29-6. 24-lead qsop o241 s 29.0 package diagrams (continued) dimensions in inches jedec std ref mo-119 51-85025-*c 0.033 0.228 0.150 0.337 0.053 0.004 0.025 0.008 0.016 0.007 0-8 ref. 0.344 0.157 0.244 bsc. 0.012 0.010 0.069 0.034 0.010 seating plane max. dimensions in inches min. pin 1 id 1 12 24 13 0.004 51-85055-*b
cy7c63310 cy7c638xx document 38-08035 rev. *i page 72 of 74 figure 29-7. 32-lead qfn package psoc is a trademark of cypress microsystems. encore is a tr ademark of cypress semiconducto r corporation. all product and company names mentioned in this document are the trademarks of their respective holders. 29.0 package diagrams (continued) 0.50 dia. 4.65 c 0.93 max. n seating plane n 2 2 0.230.05 0.50 1 1 0.05 0-12 0.30-0.50 0.05 max. c 0.20 ref. 0.80 max. pin1 id 3.50 0.420.18 (4x) 4.85 5.10 4.90 0.20 r. 0.45 3.70 3.70 4.85 4.65 4.90 5.10 3.50 top view bottom view side view dimensions in mm min. max. jedec # mo-220 package weight: 0.054 grams 51-85188-*a
cy7c63310 cy7c638xx document 38-08035 rev. *i page 73 of 74 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. 30.0 document history page document title: cy7c63310/cy7c638xx encore ? ii low-speed usb peripheral controller document number: 38-08035 rev. ecn no. issue date orig. of change description of change ** 131323 12/11/03 xgr new data sheet *a 221881 see ecn kku added register descriptions and package information, changed from advance information to preliminary *b 271232 see ecn bon reformatted updated with the latest information *c 299179 see ecn bon corrected 24-pdip pinout typo in table 5.1 added table 10-1 updated table 9-5 , table 10-3 , table 13-1 , table 17-2 , table 17-4 , ta ble 17 -6 . and table 15-2 . added various updates to the gpio section ( section 14.0 ) corrected table 15-3 . corrected figure 27-7 and figure 27-8 . added the 16-pin pdip package diagram ( section 29.0 ) *d 322053 see ecn tvr bon introduction section: last para removed low-voltage reset. there is no lvr there is only lvd (low voltage detect) . explained more about lvd and por changed capture pins from p0.0,p0.1 to p0.5,p0.6 table 6-1: changed table heading (removed mnemonics and made as register names). table 9-5: included #of rows for different flash sizes section10-1: changed cpuclk selectable options from n=0-5,7,8 to n=0-5,7 clocks section: changed itmr clk division to 1,2,3,4. updated the sources to itmrclk, tcapclks. mentioned p17 is ttl enabled permanently. corrected frt, pit data write order. updated intclr ,intmsk registers. in the register table also. dc spec sheet: changed lvr to lvd included max min program- mable trip points based on char data. updated the 50ma sink pins on 638xx, 63903. keep-alive voltage mentioned co rresponding to keep-alive current of 20ua. included notes regarding vol,voh on p1.0,p1.1 and tmdo spec. ac specs: t mdo1 , t sdo1 in description column changed phase to 0 section 5: removed the vreg from the cy7c63310 and cy7c63801 removed sclk and sdata. created a separate pinout diagram for the cy7c63813 added the gpio block diagram ( figure 14-1. ) ta ble 10 -4 : changed the sleep timer clock unit from 32 khz count to hz ta ble 21 -1 : added more descriptions to the register *e 341277 see ecn bha corrected v ih ttl value in dc characteristics table updated v il ttl value added footnote to pin description table for d+/d- pins added typical values to low voltage detect table corrected pin label on 16-pin pdip package corrected minor typos *f 408017 see ecn tyj corrected pin assignment for th e 24-pin qsop package - gpio port 3 in table 5-1: pin assignment new assignments: pin 19 assigned to p3.0 and pin 20 to p3.1 table 17.7 int_mask1 changed to 0xe1 table 17.8 int_mask0 changed to 0xe0 table 24.0-register summary, address e0 assigned to int_mask0 and address e1 assigned to int_mask1 *g 424790 see ecn tyj minor text changes to make document more readable removed cy7c639xx removed cy7c639xx from ordering information table added text concerning current draw for p0.0 and p0.1 in table 5-1 corrected figure 9-2 to represent single stack added comment about availability of 3.3v i/o on p1.3-p1.6 in table 5-1 added information on flash endurance and data retention to section 9.3 added block diagrams and timing diagrams added cy7c638xx die form diagrams, pad assignment tables and ordering information keyboard references removed cy7c63923-xc die diagram removed, removed references to the 639xx parts updated part numbers in the header
cy7c63310 cy7c638xx document 38-08035 rev. *i page 74 of 74 *h 491711 see ecn tyj minor text changes 32-qfn part added removed 638xx die diagram and die form pad assignment removed gpio port 4 configuration details corrected gpio characteristics of p0.0 an d p0.1 to p1.0 and p1.1 respectively *i 504691 see ecn tyj minor text changes removed all residual references to external crystal oscillator and gpio4 documented the dedicated 3.3v regulator for usb transceiver documented bandgap/voltage regulator behavior on wake up voltage regulator line/load regulation documented usb active and ps2 data low interrupt trigger conditions documented. gpio capacitance and timing diagram included method to clear capture interrupt status bit discussed sleep and wake up sequence documented. ep1mode/ep2mode regi ster issue discussed 30.0 document history page (continued) document title: cy7c63310/cy7c638xx encore ? ii low-speed usb peripheral controller document number: 38-08035 rev. ecn no. issue date orig. of change description of change

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